Analog Devices Inc. LTC2140IUP-12#PBF

Overview

LTC2140IUP-12#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 25Msps dual-channel simultaneous-sampling analog-to-digital converter optimized for high-dynamic-range signal digitization in communications and portable medical imaging systems. It delivers 70.5dB SNR, 89dB SFDR, and ultralow 0.10psRMS jitter at full speed, operating from a single 1.8V supply with CMOS, DDR CMOS, or DDR LVDS output options.

For engineers reviewing the LTC2140IUP-12#PBF datasheet, LTC2140IUP-12#PBF pinout, LTC2140IUP-12#PBF application, or LTC2140IUP-12#PBF equivalent, key selection criteria include its guaranteed ±0.3LSB INL over temperature, 750MHz full-power bandwidth, low 48mW total power consumption, and support for differential or single-ended clock inputs with optional duty cycle stabilization.

Technical Context

The LTC2140IUP-12#PBF implements two independent 12-bit ADC cores sharing a common sample-and-hold with 750MHz bandwidth, enabling true simultaneous sampling across channels. Its architecture supports selectable input ranges (1VP-P to 2VP-P), internal or external reference modes, and configurable digital outputs including full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS.

Control is implemented via a serial SPI port (PAR/SER = GND) or parallel logic interface (PAR/SER = VDD), supporting dynamic configuration of output format, randomizer, clock stabilizer, and power modes (Nap at 10mW, Sleep at 1mW). The device uses a 64-pin 9mm × 9mm QFN package with exposed thermal pad soldered to PCB ground.

Key Specifications

Pinout & Package

Package: 64-lead (9mm × 9mm) plastic QFN with exposed thermal pad (Pin 65 = GND, must be soldered to PCB).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, low-power ADC applications.

Compared with AD9233BCPZ-25 and LTC2246IUP-12#PBF, the LTC2140IUP-12#PBF uniquely delivers guaranteed simultaneous sampling, superior 70.5dB SNR, and integrated DDR LVDS output - making it the only option among the three that meets strict phase-coherent, low-power, wide-bandwidth requirements for portable medical and compact SDR systems.

Availability

LTC2140IUP-12#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, portable medical imaging, and software-defined radio applications requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.

Supply support for LTC2140IUP-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving precision instrumentation, communications, and industrial markets.

The LTC2140 series belongs to Linear's high-speed, low-power dual ADC product line, designed specifically for applications demanding simultaneous sampling, wide input bandwidth, and ultra-low jitter in space-constrained, thermally sensitive environments.

FAQ

What is the maximum sampling rate supported by the LTC2140IUP-12#PBF?

The LTC2140IUP-12#PBF is rated for a maximum sampling rate of 25Msps - this is the fixed top speed for the LTC2140 variant within the LTC214x-12 family (LTC2142 = 65Msps, LTC2141 = 40Msps). Operation above 25Msps is not specified and may result in degraded AC performance including reduced SNR and SFDR.

Does the LTC2140IUP-12#PBF support simultaneous sampling across both channels?

Yes, the LTC2140IUP-12#PBF implements true simultaneous sampling using a shared sample-and-hold architecture, guaranteeing sub-picosecond channel-to-channel skew. This is confirmed in the datasheet description: "2-Channel Simultaneously Sampling ADC" and verified by matching pipeline latency (6.5 cycles) and identical timing specs for both channels.

What output interface options does the LTC2140IUP-12#PBF provide?

The LTC2140IUP-12#PBF supports three digital output modes: full-rate CMOS, double-data-rate (DDR) CMOS, and DDR LVDS. Output format is selected via the PAR/SER pin and SCK configuration. CMOS outputs support OVDD from 1.2V to 1.8V; DDR LVDS includes on-chip 100Ω termination and operates with 1.75mA or 3.5mA current modes.

What is the guaranteed integral nonlinearity (INL) specification for the LTC2140IUP-12#PBF over temperature?

The LTC2140IUP-12#PBF guarantees ±0.3LSB typical INL over its full operating temperature range of –40°C to +85°C, with min/max bounds of –0.9LSB to +0.9LSB. This is explicitly stated in the "Converter Characteristics" table under "Integral Linearity Error" with the "l" symbol denoting full-temperature-range specification.

How is power managed in the LTC2140IUP-12#PBF during idle periods?

The LTC2140IUP-12#PBF provides two low-power states: Nap mode (10mW) retains register settings and reference voltage while disabling the ADC core, and Sleep mode (1mW) shuts down nearly all circuitry except basic bias generation. Both modes are controlled via the SPI interface or parallel logic pins (CS/SDI), enabling rapid wake-up (<1μs) for burst-mode acquisition.