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Analog Devices Inc. LTC2140IUP-14#PBF
- Part No.:
- LTC2140IUP-14#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LTC2140IUP-14#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 64QFN
- Quantity:
- Payment:
- Shipping:
Inventory:106
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Product details
Overview
LTC2140IUP-14#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, 25Msps dual-channel simultaneous-sampling analog-to-digital converter optimized for high-dynamic-range signal acquisition in demanding RF and instrumentation systems. It delivers 72.7dB SNR, 90dB SFDR, and ultralow 0.10psRMS jitter at 70MHz input, operating from a single 1.8V supply with 50mW total power consumption - ideal for portable medical imaging and multi-channel data acquisition.
For engineers reviewing the LTC2140IUP-14#PBF datasheet, LTC2140IUP-14#PBF pinout, LTC2140IUP-14#PBF application, or LTC2140IUP-14#PBF equivalent, key selection criteria include guaranteed ±1LSB INL over temperature, 750MHz full-power bandwidth, selectable CMOS/DDR CMOS/DDR LVDS outputs, and support for differential or single-ended clock inputs with optional duty cycle stabilization.
Technical Context
The LTC2140IUP-14#PBF implements two independent 14-bit ADC cores sharing a common sample-and-hold with 750MHz bandwidth and 0.10psRMS aperture jitter in differential encode mode. Its architecture supports simultaneous sampling across both channels with <±1.5mV offset matching and ±0.2%FS gain matching - critical for phase-coherent I/Q demodulation in SDR and base station receivers.
Digital interface flexibility includes full-rate CMOS, DDR CMOS, or DDR LVDS output modes, with separate OVDD supply enabling 1.2V–1.8V CMOS swing control. Configuration is managed via SPI-compatible serial port (CS/SCK/SDI/SDO) or parallel logic inputs, supporting shutdown and nap modes for dynamic power management.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over –40°C to +85°C - ensures monotonicity in closed-loop control and precision measurement. |
| Sampling Rate | 25Msps - enables Nyquist-limited capture of signals up to 12.5MHz without aliasing in baseband applications. |
| SNR @ 70MHz | 72.7dBFS - provides >12 effective bits for high-fidelity digitization of IF signals in communications receivers. |
| SFDR @ 70MHz | 90dBc - suppresses spurious content sufficiently for LTE/WiMAX adjacent channel rejection requirements. |
| Total Power | 50mW at 25Msps with CMOS outputs - allows thermal-constrained deployment in handheld ultrasound and portable test equipment. |
| Input Bandwidth | 750MHz full-power - supports undersampling of 2nd/3rd Nyquist zone signals up to 375MHz with minimal amplitude roll-off. |
| Aperture Jitter | 0.10psRMS (differential encode) - limits SNR degradation to <0.1dB at 140MHz input frequency. |
Pinout & Package
64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND), requiring soldering to PCB ground plane for thermal and electrical integrity. Pin functions are identical across all digital output modes (CMOS/LVDS).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (1,16,17,64) | Analog supply input | 1.7–1.9V rail powering ADC core and reference; requires local 0.1μF ceramic bypass per group. |
| AIN1+/AIN1– (4,5) | Differential analog input CH1 | Accepts 1–2VP-P input range; biased by VCM1 (Pin 2) at VDD/2 for optimal common-mode rejection. |
| ENC+/ENC– (18,19) | Differential encode clock input | Rising/falling edge-triggered sampling; ENC– tied to GND enables single-ended operation. |
| PAR/SER (11) | Programming mode select | Ground = serial SPI mode; VDD = parallel logic mode - determines CS/SCK/SDI function mapping. |
| D1_0–D1_13 / D2_0–D2_13 (25–32,45–58, etc.) | Parallel data outputs | 14-bit CMOS outputs per channel; pin grouping varies by output mode (full-rate, DDR, or LVDS differential pairs). |
| OVDD (42) | Digital output supply | 1.1–1.9V adjustable rail setting CMOS output swing or LVDS current mode (1.75/3.5mA). |
| SENSE (63) | Reference configuration | Connect to VDD for ±1V input range; to GND for ±0.5V; or to external 0.625–1.3V reference for custom scaling. |
Key Features
| Feature | Design Value |
|---|---|
| Simultaneous sampling dual ADC | Guaranteed <1ps inter-channel skew enables coherent I/Q sampling without calibration overhead. |
| Configurable output interface | Hardware-selectable CMOS/DDR CMOS/DDR LVDS eliminates need for external level translators in FPGA interfacing. |
| Internal reference with external option | 1.25V ±25ppm/°C VREF output and SENSE-pin programmable input range reduce BOM count and layout complexity. |
| Low-power sleep/nap modes | 1mW sleep and 10mW nap modes allow rapid wake-up (<1μs) for burst-mode acquisition in battery-powered instruments. |
| Serial SPI configuration port | Full register access via 4-wire interface enables runtime reconfiguration of output format, randomizer, and clock stabilizer. |
Applications
| Portable Medical Imaging | Multi-Channel Data Acquisition |
|---|---|
Use Scenario: Ultrasound beamforming subsystem digitizing echo return signals from 16–64 transducer elements. IC Role / Device Role / Timing Role: Dual-channel simultaneous sampling ADC capturing I/Q baseband data with matched gain/offset for real-time phase alignment. Use Value: 72.7dB SNR and 90dB SFDR preserve tissue contrast resolution; 50mW power enables integration into handheld probes. | Use Scenario: Industrial vibration monitoring system acquiring synchronized acceleration data from multiple sensors on rotating machinery. IC Role / Device Role / Timing Role: Simultaneous sampling front-end providing time-aligned 14-bit samples across two sensor channels for FFT-based fault detection. Use Value: <±1.5mV offset matching and <1ps inter-channel skew eliminate phase-induced spectral leakage in spectral analysis. |
| Nondestructive Testing | Software Defined Radios |
Use Scenario: Eddy-current inspection instrument digitizing high-frequency return signals from conductive materials. IC Role / Device Role / Timing Role: High-bandwidth ADC capturing transient reflections with 750MHz full-power bandwidth and low aperture jitter. Use Value: 0.10psRMS jitter preserves time-domain fidelity for defect localization; 25Msps rate supports 12.5MHz analysis bandwidth. | Use Scenario: Wideband SDR receiver downconverting and digitizing multiple RF bands simultaneously using direct sampling architecture. IC Role / Device Role / Timing Role: Dual ADC performing undersampling of 70MHz IF signals with 90dB SFDR to reject adjacent channel interference. Use Value: 750MHz input bandwidth and 90dB SFDR enable clean capture of wide instantaneous bandwidths without image-reject filtering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9257BCPZ-25 | 14-bit, 25Msps, single-supply 1.8V, but only 69.5dB SNR and 85dB SFDR at 70MHz; no internal reference; LVDS-only outputs. | Lower dynamic range limits use in high-fidelity medical imaging; requires external reference and level-shifting for CMOS FPGAs. | Select when LVDS interface and lower cost outweigh SNR/SFDR requirements. |
| ADS52J90IRGCT | 14-bit, 25Msps, 1.8V supply, 73.5dB SNR, 89dB SFDR, but uses JESD204B serial interface instead of parallel outputs; higher 125mW power. | Requires JESD204B-capable FPGA; unsuitable for legacy parallel-bus designs; better for high-channel-count systems with serializer consolidation. | Select when migrating to JESD204B infrastructure and multi-device synchronization is required. |
Compared with AD9257BCPZ-25 and ADS52J90IRGCT, the LTC2140IUP-14#PBF offers superior SFDR (90dB vs. 85/89dB) and integrated reference flexibility, while maintaining lower power (50mW) and parallel CMOS compatibility - making it optimal for space-constrained, high-fidelity dual-channel acquisition where signal integrity is critical.
Availability
LTC2140IUP-14#PBF is available at Aetrix Electronics and suitable for portable medical imaging, multi-channel data acquisition, nondestructive testing, and software defined radios requiring stable component supply across industrial temperature ranges.
Supply support for LTC2140IUP-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance signal chain portfolio, emphasizing precision analog, RF, and mixed-signal ICs for demanding measurement and communication applications.
The LTC2140IUP-14#PBF belongs to the LTC214x family of dual-channel simultaneous-sampling ADCs designed specifically for high-dynamic-range, low-power digitization in communications infrastructure, portable instrumentation, and phased-array sensing systems.
FAQ
What is the maximum input frequency supported by the LTC2140IUP-14#PBF?
The LTC2140IUP-14#PBF features a 750MHz full-power bandwidth, meaning it can accurately digitize analog inputs up to 750MHz without significant amplitude attenuation. This enables undersampling applications where IF signals in the second or third Nyquist zone (e.g., 140MHz at 25Msps) are captured directly, reducing front-end filtering complexity in SDR and test equipment designs using the LTC2140IUP-14#PBF.
Does the LTC2140IUP-14#PBF support both differential and single-ended clock inputs?
Yes, the LTC2140IUP-14#PBF supports both configurations via the ENC+ and ENC– pins. In differential mode, a 2VP-P sine wave applied across ENC+/ENC– achieves 0.10psRMS jitter. In single-ended mode, ENC– is tied to GND and ENC+ accepts TTL, CMOS, or PECL-compatible signals - enabling flexible clock tree integration without external differential receivers in the LTC2140IUP-14#PBF design.
How does the SENSE pin affect the input range of the LTC2140IUP-14#PBF?
The SENSE pin on the LTC2140IUP-14#PBF selects the full-scale input range: connecting SENSE to VDD configures ±1V (2VP-P), tying it to GND sets ±0.5V (1VP-P), and applying an external 0.625–1.3V reference enables custom scaling. This hardware-selectable range eliminates firmware configuration overhead and ensures deterministic analog performance across temperature - a key feature distinguishing the LTC2140IUP-14#PBF from fixed-range alternatives.
What output interface options does the LTC2140IUP-14#PBF provide?
The LTC2140IUP-14#PBF supports three parallel output modes: full-rate CMOS, double-data-rate (DDR) CMOS, and DDR LVDS - selected via SCK in parallel programming mode or SPI register in serial mode. CMOS outputs operate from 1.2–1.8V OVDD for FPGA compatibility, while DDR LVDS provides noise-immune transmission at 3.5mA or 1.75mA current levels - giving designers interface flexibility without external translators in the LTC2140IUP-14#PBF implementation.
Is the LTC2140IUP-14#PBF pin-compatible with other members of the LTC214x family?
Yes, the LTC2140IUP-14#PBF shares identical 64-pin QFN packaging, pinout, and footprint with LTC2141IUP-14#PBF (40Msps) and LTC2142IUP-14#PBF (65Msps). This allows drop-in speed upgrades within the same PCB layout - for example, replacing LTC2140IUP-14#PBF with LTC2141IUP-14#PBF increases sampling rate to 40Msps while retaining all analog and digital connections, simplifying design scalability in the LTC2140IUP-14#PBF platform.
LTC2140IUP-14#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 25M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-QFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2140IUP-14#PBF FAQ
1.How can I place an order for LTC2140IUP-14#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2140IUP-14#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2140IUP-14#PBF reliable?
The price and inventory of LTC2140IUP-14#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2140IUP-14#PBF is usually 5 days.
3.What payment methods are accepted for LTC2140IUP-14#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2140IUP-14#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2140IUP-14#PBF?
LTC2140IUP-14#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2140IUP-14#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2140IUP-14#PBF?
For technical support, including LTC2140IUP-14#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2140IUP-14#PBF requirements.
6.How does Aetrix verify that LTC2140IUP-14#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2140IUP-14#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2140IUP-14#PBF meets industry standards.
7.What is the process for return or replacement of LTC2140IUP-14#PBF?
All LTC2140IUP-14#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2140IUP-14#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2140IUP-14#PBF part is unused and in its original packaging.
Return procedure for LTC2140IUP-14#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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