Analog Devices Inc. LTC2144IUP-14#PBF

Overview

LTC2144IUP-14#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, dual-channel, simultaneous-sampling analog-to-digital converter optimized for high-frequency signal digitization in communications infrastructure. It delivers 72.9dB SNR and 90dB SFDR at 105Msps sampling rate with 750MHz full-power bandwidth, operates from a single 1.8V supply, and supports CMOS, DDR CMOS, or DDR LVDS digital outputs.

For engineers reviewing the LTC2144IUP-14#PBF datasheet, LTC2144IUP-14#PBF pinout, LTC2144IUP-14#PBF application, or LTC2144IUP-14#PBF equivalent, key selection considerations include its 105Msps dual-channel throughput, ±1LSB INL, low 149mW total power dissipation, and support for differential or single-ended clock inputs with optional duty cycle stabilization.

Technical Context

The LTC2144IUP-14#PBF implements two independent 14-bit ADC cores sharing a common sample-and-hold with 0.08psRMS jitter, enabling precise undersampling of IF signals up to 140MHz. Its architecture includes programmable input range selection (1VP-P to 2VP-P), internal/external reference options, and configurable output modes including full-rate CMOS, DDR CMOS, and DDR LVDS.

Digital configuration is handled via a serial SPI port supporting register readback, while hardware control pins (CS, SCK, SDI) enable parallel programming mode. Power management includes Nap (16mW) and Sleep (1mW) modes, and the ENC+/ENC– interface accepts PECL, LVDS, TTL, or CMOS clock sources with optional duty cycle stabilization.

Key Specifications

Pinout & Package

64-lead (9mm × 9mm) plastic QFN package with exposed ground pad (Pin 65), requiring soldering to PCB ground for thermal and electrical integrity. Pin functions are defined per digital output mode (CMOS/LVDS); shared pins include VDD (1,16,17,64), GND (3,6,14), AIN1± (4,5), AIN2± (12,13), ENC+ (18), ENC– (19), PAR/SER (11), CS (20), SCK (21), SDI (22), OVDD (42), OGND (41), VREF (62), SENSE (63), and SDO (61).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 14-bit ADC applications.

Compared with AD9250BCPZ-105 and ADS52J90IRGCT, the LTC2144IUP-14#PBF provides the lowest power (149mW), widest input range configurability (1–2VP-P), and most flexible digital interface options (CMOS/DDR CMOS/DDR LVDS), making it optimal for space- and power-constrained dual-channel digitizers.

Availability

LTC2144IUP-14#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, portable medical imaging, and multi-channel data acquisition systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for LTC2144IUP-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2144IUP-14#PBF belongs to ADI's high-speed precision ADC product line, designed specifically for demanding communications and instrumentation applications requiring simultaneous sampling, low power, and exceptional dynamic range.

FAQ

What is the maximum sampling rate supported by the LTC2144IUP-14#PBF?

The LTC2144IUP-14#PBF supports a maximum sampling rate of 105Msps, as specified in its ordering part number suffix "-14" and confirmed in the Electrical Characteristics table. This rate applies to both channels simultaneously and is validated across the full –40°C to +85°C operating temperature range with guaranteed AC performance including 72.9dB SNR and 90dB SFDR.

Does the LTC2144IUP-14#PBF support differential clock inputs?

Yes, the LTC2144IUP-14#PBF supports fully differential encode clock inputs via ENC+ (Pin 18) and ENC– (Pin 19), with 0.08psRMS jitter enabling high-fidelity undersampling. It also supports single-ended operation when ENC– is tied to GND, and includes an optional duty cycle stabilizer to maintain performance with non-50% duty cycle clocks.

What input voltage ranges does the LTC2144IUP-14#PBF support, and how are they selected?

The LTC2144IUP-14#PBF supports selectable input ranges of 1VP-P to 2VP-P using the SENSE pin (Pin 63): grounding SENSE selects ±0.5V range, connecting to VDD selects ±1V range, and applying 0.625V–1.3V externally sets ±0.8×V_SENSE. This configurability allows optimization for signal chain dynamic range without changing external components.

Can the LTC2144IUP-14#PBF interface directly with an FPGA using LVDS outputs?

Yes, the LTC2144IUP-14#PBF supports DDR LVDS outputs with 100Ω on-chip termination and programmable 1.75mA or 3.5mA drive strength. Its LVDS outputs meet ANSI TIA/EIA-644-A specifications and interface directly with Xilinx and Intel FPGA LVDS I/O banks without external termination resistors when enabled.

What power-saving modes are available on the LTC2144IUP-14#PBF?

The LTC2144IUP-14#PBF offers three power states: Active (149mW at 105Msps), Nap mode (16mW), and Sleep mode (1mW). These are controlled via SPI register writes or hardware pins (CS/SDI), enabling dynamic power scaling in portable or thermally constrained applications while retaining fast wake-up capability.