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Analog Devices Inc. LTC2155CUP-12#PBF
- Part No.:
- LTC2155CUP-12#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LTC2155CUP-12#PBF.pdf
- Description:
- IC ADC 12BIT PIPELINED 64QFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,151
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Product details
Overview
LTC2155CUP-12#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, 12-bit, 170Msps analog-to-digital converter optimized for high-frequency undersampling in communications and instrumentation systems. It delivers 68.3dB SNR, 90dB SFDR, 1.25GHz full-power bandwidth, single 1.8V supply operation, and DDR LVDS outputs - enabling direct digitization of IF signals up to 907MHz in cellular basestations and software-defined radios.
For engineers reviewing the LTC2155CUP-12#PBF datasheet, LTC2155CUP-12#PBF pinout, LTC2155CUP-12#PBF application, or LTC2155CUP-12#PBF equivalent, this page provides verified specifications, package mapping, functional pin roles, real-world use cases, and validated alternative options for RF receiver front-end design, medical imaging data acquisition, and high-definition video digitization.
Technical Context
The LTC2155CUP-12#PBF implements a pipelined ADC architecture with integrated sample-and-hold (S/H) and correction logic, supporting simultaneous dual-channel sampling at up to 170Msps. Its 1.25GHz input bandwidth enables wideband undersampling without external anti-aliasing filters for frequencies up to 907MHz.
It features programmable LVDS output current (1.75mA or 3.5mA), optional clock duty cycle stabilizer, SPI-configurable sleep/nap modes, and flexible reference selection via SENSE pin - allowing ±0.75V internal or ±0.6×VSENSE external input ranges with 1.5VP-P differential drive capability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in precision measurement applications. |
| Sampling Rate | 170Msps maximum - supports real-time digitization of wideband IF signals in SDR and test equipment. |
| SNR / SFDR | 68.3dB SNR and 90dB SFDR at 70MHz input - ensures high dynamic range for detecting weak signals amid strong interferers. |
| Full-Power Bandwidth | 1.25GHz - enables direct RF sampling of L-band and S-band signals without downconversion. |
| Power Consumption | 545mW total at 170Msps (3.5mA LVDS mode) - balances performance and thermal management in dense PCB layouts. |
| Analog Input Range | 1.5VP-P differential - simplifies interface with transformer-coupled or balun-driven RF front-ends. |
| Supply Voltage | Single 1.8V analog (VDD) and digital (OVDD) supply - reduces power delivery complexity and improves noise isolation. |
Pinout & Package
64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (1,2,15,16,17,64) | Analog power supply | 1.8V supply for ADC core and S/H; each group requires local 0.1µF ceramic bypass to GND. |
| AINA+/AINA– (4,5), AINB+/AINB– (12,13) | Differential analog inputs | Two independent 1.5VP-P input channels; common-mode bias set by VCM pin. |
| ENC+/ENC– (19,20) | Encode clock inputs | Differential sampling clock interface accepting sine wave, LVDS, PECL, TTL, or CMOS; supports optional duty cycle stabilization. |
| DA0_1+/- to DA10_11+/- (44–45,46–47,50–51,52–53,54–55,56–57), DB0_1+/- to DB10_11+/- (26–27,28–29,30–31,34–35,36–37,38–39) | DDR LVDS data outputs | 12-bit dual-channel data multiplexed across 6 differential pairs per channel; even/odd bits time-multiplexed on CLKOUT edges. |
| CLKOUT+/CLKOUT– (40,41) | Data output clock | Synchronized DDR clock for LVDS data capture; phase programmable via SPI register. |
| PAR/SER (63), CS (62), SCK (61), SDI (60), SDO (59) | Configuration interface | Selects serial (SPI) or parallel programming mode; controls LVDS current, sleep mode, and duty cycle stabilizer. |
| OF+/OF– (22,23) | Overflow/underflow flag | Indicates saturation on either channel A or B - critical for AGC loop feedback in receiver systems. |
Key Features
| Feature | Design Value |
|---|---|
| 1.25GHz full-power bandwidth | Enables direct sampling of 907MHz signals at –1dBFS without external filtering or frequency translation. |
| 6-cycle pipeline latency | Minimizes timing uncertainty in closed-loop systems such as digital predistortion (DPD) and adaptive beamforming. |
| Programmable LVDS output current (1.75mA / 3.5mA) | Allows optimization of signal integrity vs. power: 1.75mA reduces EMI and crosstalk in high-density routing. |
| Internal 100Ω on-chip LVDS termination | Eliminates need for external resistors on each differential pair - saves board space and improves impedance matching. |
| Optional clock duty cycle stabilizer | Compensates for asymmetric clock sources (e.g., PLL outputs), maintaining AC performance at full 170Msps rate. |
| Low-power nap mode (154mW) | Reduces power by >70% during idle periods while retaining configuration and enabling fast wake-up (<1µs). |
Applications
| Cellular Basestation Receiver | Medical Ultrasound Imaging |
|---|---|
|
Use Scenario: Digitizing 122–171MHz IF signals from multi-carrier WCDMA/LTE receivers with high adjacent-channel rejection requirements. IC Role / Device Role / Timing Role: Dual-channel ADC capturing I/Q baseband data at 170Msps with 90dB SFDR to resolve weak user signals near strong interferers. Use Value: 1.25GHz bandwidth eliminates analog pre-filtering stages; DDR LVDS outputs interface directly to FPGA transceivers with minimal layout complexity. |
Use Scenario: High-speed echo signal acquisition in portable ultrasound systems requiring >65dB dynamic range across 5–15MHz bandwidth. IC Role / Device Role / Timing Role: Simultaneous sampling of two receive channels for beamforming, leveraging low 0.54LSBRMS transition noise. Use Value: 68.3dB SNR at 170Msps enables detection of low-amplitude tissue reflections; 1.8V single supply simplifies power architecture in battery-powered units. |
| High-Definition Video Digitization | Test & Measurement Instrumentation |
|
Use Scenario: Capturing uncompressed 1080p60 video streams with minimal quantization distortion for broadcast-grade analysis. IC Role / Device Role / Timing Role: Dual ADC digitizing Y/C or RGB components at 170Msps with precise timing alignment between channels. Use Value: ±0.30LSB INL and ±0.16LSB DNL ensure accurate color fidelity and gamma reproduction without post-processing correction. |
Use Scenario: Real-time spectrum analysis in benchtop analyzers requiring wide instantaneous bandwidth and spurious-free operation. IC Role / Device Role / Timing Role: Front-end ADC providing 90dB SFDR and <0.15ps RMS aperture jitter for accurate harmonic and intermodulation measurement. Use Value: Low 545mW power dissipation allows integration into compact, fanless enclosures without thermal derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 12-bit, high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9233BCPZ-170 | 12-bit, 170Msps, single-channel only; 70dB SNR, 85dB SFDR; requires external clock buffer and LVDS termination. | Lacks dual-channel synchronization and integrated duty cycle stabilizer - unsuitable for I/Q or time-aligned dual-signal capture. | Select when single-channel performance suffices and board space permits external support components. |
| LTC2156CUP-12#PBF | Same pinout and feature set, but rated for 210Msps sampling; higher power (592mW) and slightly improved SFDR (90.1dB). | Direct drop-in upgrade path for designs needing higher Nyquist zone coverage or margin in undersampling applications. | Choose when system clock budget allows 210Msps and SNR/SFDR margin above 68.3dB/90dB is required. |
Compared with AD9233BCPZ-170, LTC2155CUP-12#PBF provides synchronized dual-channel operation and integrated clock conditioning; compared with LTC2156CUP-12#PBF, it trades 40Msps speed for lower power and thermal load - making it optimal for cost- and power-sensitive 170Msps systems.
Availability
LTC2155CUP-12#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, medical imaging, and high-definition video digitization requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC2155CUP-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance signal chain portfolio, emphasizing precision, speed, and power efficiency for demanding analog applications.
The LTC2155CUP-12#PBF belongs to the LTC215x family of dual high-speed ADCs designed specifically for wideband communications, instrumentation, and imaging systems where dynamic range, bandwidth, and low-latency sampling are critical.
FAQ
What is the maximum sampling rate supported by the LTC2155CUP-12#PBF?
The LTC2155CUP-12#PBF supports a maximum sampling rate of 170Msps. This is specified under recommended operating conditions (VDD = OVDD = 1.8V, differential ENC+/ENC– = 2VP-P sine wave). At this rate, the device achieves 68.3dB SNR and 90dB SFDR at 70MHz input frequency, with full 12-bit resolution and no missing codes across the 0°C to 70°C operating temperature range.
Does the LTC2155CUP-12#PBF require external termination resistors for its LVDS outputs?
No, the LTC2155CUP-12#PBF includes an optional internal 100Ω termination resistor between each LVDS output pair (e.g., DA0_1+, DA0_1–), configurable via SPI register. When enabled, this eliminates the need for external termination, reducing PCB area and improving impedance control. External 100Ω termination is only required if the internal option is disabled and system-level signal integrity demands it.
How does the SENSE pin configure the input range on the LTC2155CUP-12#PBF?
The SENSE pin on the LTC2155CUP-12#PBF selects the reference mode: connecting SENSE to VDD enables the internal 1.25V reference and sets the input range to ±0.75V (1.5VP-P). Applying an external voltage between 1.2V and 1.3V to SENSE selects an input range of ±0.6 × VSENSE, allowing precise scaling for custom front-end gain stages - for example, 1.25V on SENSE yields ±0.75V, matching the nominal VREF output.
Can the LTC2155CUP-12#PBF operate with a non-50% duty cycle clock?
Yes, the LTC2155CUP-12#PBF includes an optional clock duty cycle stabilizer that can be enabled via SPI configuration. When active, it corrects duty cycle deviations in the ENC+/ENC– input clock, maintaining full AC performance (68.3dB SNR, 90dB SFDR) even with duty cycles as low as 1.5ns high/low time asymmetry - essential when using PLL-based or crystal oscillator-derived clocks with inherent skew.
What is the pipeline latency of the LTC2155CUP-12#PBF, and why does it matter?
The LTC2155CUP-12#PBF has a fixed pipeline latency of six clock cycles from encode edge to valid DDR LVDS data output. This deterministic delay is critical for time-sensitive applications like digital predistortion (DPD) in power amplifiers or real-time beam steering, where firmware or FPGA logic must align feedback paths with known, repeatable timing offsets - enabling precise loop compensation without variable jitter.
LTC2155CUP-12#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 170M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 64-QFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2155CUP-12#PBF FAQ
1.How can I place an order for LTC2155CUP-12#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2155CUP-12#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2155CUP-12#PBF reliable?
The price and inventory of LTC2155CUP-12#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2155CUP-12#PBF is usually 5 days.
3.What payment methods are accepted for LTC2155CUP-12#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2155CUP-12#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2155CUP-12#PBF?
LTC2155CUP-12#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2155CUP-12#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2155CUP-12#PBF?
For technical support, including LTC2155CUP-12#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2155CUP-12#PBF requirements.
6.How does Aetrix verify that LTC2155CUP-12#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2155CUP-12#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2155CUP-12#PBF meets industry standards.
7.What is the process for return or replacement of LTC2155CUP-12#PBF?
All LTC2155CUP-12#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2155CUP-12#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2155CUP-12#PBF part is unused and in its original packaging.
Return procedure for LTC2155CUP-12#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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