Analog Devices Inc. LTC2155IUP-14
- Part No.:
- LTC2155IUP-14
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LTC2155IUP-14.pdf
- Description:
- IC ADC 14BIT PIPELINED 64QFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,893
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Product details
Overview
LTC2155IUP-14 from Analog Devices (formerly Linear Technology) is a dual-channel, simultaneous-sampling 14-bit analog-to-digital converter with 170Msps sampling rate, 70dB SNR, 90dB SFDR, and 1.25GHz full-power input bandwidth. It operates from a single 1.8V supply, features DDR LVDS outputs, and targets high-frequency signal digitization in communications infrastructure.
For engineers reviewing the LTC2155IUP-14 datasheet, LTC2155IUP-14 pinout, LTC2155IUP-14 application, or LTC2155IUP-14 equivalent, key selection criteria include its guaranteed ±0.85LSB INL over temperature, low 567mW total power at 170Msps, 64-pin QFN package with exposed thermal pad, and support for both internal and external reference modes.
Technical Context
The LTC2155IUP-14 implements a pipelined ADC architecture with integrated sample-and-hold, correction logic, and DDR LVDS output drivers. Its clock input accepts differential ENC+/ENC– signals with optional duty cycle stabilization, enabling robust timing across wide duty cycle ranges.
It supports two programming modes via PAR/SER pin: serial SPI interface (CS/SCK/SDI/SDO) for full configuration, or parallel mode for simplified control of LVDS current, sleep mode, and duty cycle stabilizer. Channel A and B outputs are fully independent, with multiplexed 14-bit DDR data per channel on dedicated differential pairs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over temperature - ensures monotonicity and full code coverage in precision measurement systems. |
| Sampling Rate | 170Msps maximum - enables Nyquist sampling of signals up to 85MHz or undersampling of RF carriers up to 1.25GHz. |
| SNR / SFDR | 70dB SNR and 90dB SFDR at 15MHz input - delivers high dynamic range for baseband and IF digitization in SDR and test equipment. |
| Power Consumption | 567mW total at 170Msps (305mA analog + 73mA digital) - optimized for thermally constrained high-density boards. |
| Analog Input Range | 1.5VP-P differential with ±0.75V swing when using internal reference - simplifies front-end driver design with rail-to-rail compatible amplifiers. |
| Full-Power Bandwidth | 1.25GHz - supports direct RF sampling of cellular, WiFi, and radar bands without external IF translation. |
| Latency | 6 clock cycles - enables deterministic real-time processing in closed-loop control and digital predistortion applications. |
Pinout & Package
64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND), requiring soldering to PCB ground for thermal and electrical performance. Pin pitch: 0.5mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Pins 1,2,15,16,17,64) | Analog power supply | 1.8V ±0.1V analog rail; requires local 0.1µF ceramic bypass per group to ensure low-noise conversion performance. |
| AINA+/AINA– (Pins 4,5) | Differential analog input, Channel A | Accepts 1.5VP-P differential signal; common-mode bias set by VCM output (Pin 10) at ~0.783V nominal. |
| ENC+/ENC– (Pins 19,20) | Differential encode clock input | Edge-triggered sampling; supports sine wave, PECL, LVDS, TTL, or CMOS drive; optional duty cycle stabilizer improves jitter tolerance. |
| DA0_1+ / DA0_1– to DA12_13+ / DA12_13– (Pins 42–43,44–45,46–47,50–51,52–53,54–55,56–57) | DDR LVDS data outputs, Channel A | Seven differential pairs carry 14-bit data (even bits on CLKOUT+ low, odd bits on high); programmable 1.75mA/3.5mA output current. |
| DB0_1+ / DB0_1– to DB12_13+ / DB12_13– (Pins 24–25,26–27,28–29,30–31,34–35,36–37,38–39) | DDR LVDS data outputs, Channel B | Independent dual-channel output path; identical timing and drive capability as Channel A for synchronous dual-channel acquisition. |
| CLKOUT+/CLKOUT– (Pins 40,41) | Data output clock | Source-synchronous DDR clock aligned to data edges; phase delay programmable via SPI to compensate for board skew. |
| PAR/SER (Pin 63) | Programming mode select | Ground = serial SPI mode (full register access); VDD = parallel mode (simplified control of LVDS current, sleep, and duty cycle stabilizer). |
Key Features
| Feature | Design Value |
|---|---|
| Dual simultaneous sampling | Guarantees precise time alignment between Channel A and B for I/Q demodulation and phased-array beamforming without inter-channel skew. |
| Internal 1.25V reference with ±30ppm/°C drift | Eliminates need for external reference IC in cost-sensitive designs while maintaining 70dB SNR across –40°C to 85°C industrial temperature range. |
| Programmable LVDS output current (1.75mA / 3.5mA) | Enables optimization of signal integrity and power: lower current reduces EMI and crosstalk on dense PCBs; higher current improves noise margin over longer traces. |
| Sleep and Nap low-power modes | Sleep mode draws <5mW (clock disabled); Nap mode draws 184mW at full speed - extends uptime in battery-backed instrumentation and portable test gear. |
| 6-cycle pipeline latency | Provides deterministic, minimal delay for real-time feedback loops in digital predistortion (DPD) and adaptive filtering applications. |
Applications
| Cellular Basestation Receiver | Software Defined Radio (SDR) |
|---|---|
|
Use Scenario: Digitizing dual-channel IF or direct-RF signals from antenna arrays in LTE/5G macrocells. IC Role / Device Role / Timing Role: Dual-channel ADC capturing synchronized I/Q data streams at 170Msps with <6-cycle latency for real-time MIMO processing. Use Value: 90dB SFDR suppresses adjacent channel interference; 1.25GHz bandwidth enables direct sampling of 3.5GHz n78 band without analog downconversion. |
Use Scenario: Reconfigurable wideband receiver in military comms or spectrum monitoring systems. IC Role / Device Role / Timing Role: High-dynamic-range digitizer supporting multiple modulation schemes (OFDM, QAM, FSK) across 10kHz–1GHz. Use Value: 70dB SNR ensures accurate constellation recovery; SPI programmability allows runtime adaptation of LVDS current and reference mode. |
| Medical Ultrasound Beamformer | High-Speed Test & Measurement |
|
Use Scenario: Acquiring echo return signals from multi-element transducer arrays with precise time-of-flight resolution. IC Role / Device Role / Timing Role: Simultaneous sampling ADC providing matched gain/phase response across dual receive channels for coherent beam synthesis. Use Value: ±0.85LSB INL guarantees linearity critical for harmonic imaging; low 1.82LSBRMS transition noise preserves weak echo fidelity. |
Use Scenario: Digitizing fast transient waveforms in oscilloscopes, arbitrary waveform analyzers, and bit error ratio testers. IC Role / Device Role / Timing Role: High-speed acquisition engine delivering 14-bit resolution at 170Msps with deterministic 6-cycle latency for trigger-to-capture timing. Use Value: 567mW power enables integration into compact benchtop instruments; DDR LVDS outputs reduce pin count vs. parallel CMOS interfaces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9257BCPZ-170 | Single-channel 14-bit 170Msps ADC; 65dB SNR, 82dB SFDR; 1.8V supply; serial LVDS outputs (not DDR). | Requires two devices for dual-channel operation; lacks simultaneous sampling guarantee and inter-channel matching specs. | Select when channel independence is acceptable and board space allows dual placement; verify layout symmetry for timing alignment. |
| LTC2156IUP-14 | Pin-compatible dual-channel 14-bit 210Msps ADC; same 64-QFN package; 70dB SNR, 90dB SFDR; 616mW power at 210Msps. | Higher speed suits wider instantaneous bandwidth applications (e.g., 100MHz IF capture); increased power and thermal load. | Choose when system requires >170Msps sampling; confirm thermal management supports 616mW dissipation in same footprint. |
Compared with AD9257BCPZ-170 and LTC2156IUP-14, the LTC2155IUP-14 uniquely balances dual-channel simultaneity, industrial temperature rating, and sub-600mW power at 170Msps - making it optimal for space-constrained, thermally sensitive, and phase-coherent applications where exact channel matching is mandatory.
Availability
LTC2155IUP-14 is available at Aetrix Electronics and suitable for cellular basestation receivers, software-defined radios, medical ultrasound systems, and high-speed test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC2155IUP-14 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC2155IUP-14 belongs to ADI's high-speed precision ADC product line, designed specifically for demanding communications and instrumentation applications requiring simultaneous dual-channel sampling, wide input bandwidth, and low power at 14-bit resolution.
FAQ
What is the operating temperature range for the LTC2155IUP-14?
The LTC2155IUP-14 is rated for industrial operation from –40°C to +85°C, as indicated by the "I" grade in the part number. This range is validated across all key specifications including SNR, SFDR, INL, and power consumption, ensuring reliable performance in base station outdoor units, industrial test gear, and medical equipment enclosures.
Does the LTC2155IUP-14 support external reference voltage?
Yes, the LTC2155IUP-14 supports external reference via the SENSE pin (Pin 7). Applying 1.200V to 1.300V to SENSE selects external reference mode, setting the analog input range to ±0.6 × VSENSE. This enables precise scaling for custom front-end gain stages and improves system-level accuracy when paired with ultra-stable external references.
How is the DDR LVDS output timing controlled on the LTC2155IUP-14?
The LTC2155IUP-14 uses source-synchronous DDR LVDS timing: data transitions align with both rising and falling edges of CLKOUT+, and the phase of CLKOUT+ relative to data can be digitally delayed via SPI-programmable registers. This allows board-level skew compensation without requiring complex FPGA delay tuning.
Can the LTC2155IUP-14 operate with a single-ended clock input?
No - the LTC2155IUP-14 requires differential clock inputs (ENC+/ENC–) for optimal jitter performance and specified AC characteristics. While the datasheet notes compatibility with TTL/CMOS logic levels, those must still be applied differentially across the ENC+/ENC– pair; single-ended drive degrades SNR and increases aperture jitter beyond spec limits.
What is the function of the PAR/SER pin on the LTC2155IUP-14?
The PAR/SER pin (Pin 63) selects the programming interface mode: grounded for full-featured serial SPI control (CS/SCK/SDI/SDO), or tied to VDD for simplified parallel mode where CS, SCK, and SDI become discrete logic inputs controlling LVDS current, sleep mode, and duty cycle stabilizer - reducing MCU GPIO usage in resource-constrained designs.
LTC2155IUP-14 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 170M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-QFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2155IUP-14 FAQ
1.How can I place an order for LTC2155IUP-14 through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2155IUP-14 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2155IUP-14 reliable?
The price and inventory of LTC2155IUP-14 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2155IUP-14 is usually 5 days.
3.What payment methods are accepted for LTC2155IUP-14?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2155IUP-14 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2155IUP-14?
LTC2155IUP-14 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2155IUP-14 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2155IUP-14?
For technical support, including LTC2155IUP-14 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2155IUP-14 requirements.
6.How does Aetrix verify that LTC2155IUP-14 is sourced from the original manufacturer or authorized distributors?
All LTC2155IUP-14 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2155IUP-14 meets industry standards.
7.What is the process for return or replacement of LTC2155IUP-14?
All LTC2155IUP-14 units undergo pre-shipment inspection (PSI). If there is an issue with LTC2155IUP-14, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2155IUP-14 part is unused and in its original packaging.
Return procedure for LTC2155IUP-14:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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