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Analog Devices Inc. LTC2156IUP-14#PBF
- Part No.:
- LTC2156IUP-14#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LTC2156IUP-14#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 64QFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,279
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Product details
Overview
LTC2156IUP-14#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, 14-bit, 210Msps analog-to-digital converter optimized for high-frequency undersampling in communications infrastructure. It delivers 70dB SNR, 90dB SFDR, and 1.25GHz full-power bandwidth with DDR LVDS outputs, operating from a single 1.8V supply and supporting low-power Nap/Sleep modes. It is used in cellular basestations and software-defined radios requiring simultaneous sampling of wideband RF signals.
For engineers reviewing the LTC2156IUP-14#PBF datasheet, LTC2156IUP-14#PBF pinout, LTC2156IUP-14#PBF application, or LTC2156IUP-14#PBF equivalent, key selection criteria include its guaranteed ±0.85LSB INL over temperature, 616mW total power at 210Msps, 6-cycle pipeline latency, and compatibility with differential sine-wave, LVDS, or CMOS clock inputs - all within a 64-pin 9mm × 9mm QFN package.
Technical Context
The LTC2156IUP-14#PBF employs a pipelined ADC architecture with integrated sample-and-hold and correction logic, enabling simultaneous sampling across two channels with matched timing and crosstalk < –95dB. Its 1.25GHz input bandwidth supports IF sampling up to 315MHz without performance degradation.
It features a programmable DDR LVDS output interface with selectable 1.75mA/3.5mA current drive, on-chip 100Ω termination, and configurable clock duty cycle stabilization. The SPI port allows runtime configuration of operating modes including Nap mode (198mW), Sleep mode (<5mW), and LVDS current level.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over –40°C to +85°C - ensures monotonicity and full code coverage in precision measurement systems. |
| Sampling Rate | 210Msps maximum - enables digitization of wide instantaneous bandwidths in SDR and test equipment. |
| SNR / SFDR | 70dB / 90dB at 15MHz input - provides high dynamic range for detecting weak signals amid strong interferers. |
| Full-Power Bandwidth | 1.25GHz - supports direct RF sampling of L-band and S-band signals without external amplification or filtering. |
| Power Consumption | 616mW total at 210Msps (350mA VDD + 85mA OVDD) - balances performance and thermal management in dense RF front-ends. |
| INL / DNL | ±0.85LSB / ±0.25LSB typical - guarantees accurate amplitude fidelity for calibration-critical applications like medical imaging. |
| Pipeline Latency | 6 clock cycles - enables deterministic timing alignment in closed-loop feedback or real-time digital predistortion. |
Pinout & Package
64-pin (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Pins 1,2,15,16,17,64) | Analog supply input | 1.8V ±0.1V analog core supply; each group requires local 0.1µF ceramic bypass to GND. |
| AINA+/AINA– (Pins 4,5) | Differential analog input, Channel A | Accepts 1.5VP-P differential signal with common-mode bias set by VCM; supports DC-coupled or AC-coupled interfaces. |
| ENC+/ENC– (Pins 19,20) | Differential encode clock input | Edge-triggered sampling clock; accepts sine wave, LVDS, PECL, TTL, or CMOS; duty cycle stabilizer optional. |
| DA0_1+ / DA0_1– (Pins 42,43) | DDR LVDS output, Channel A bits 0–1 | Even bits (DA0) appear when CLKOUT+ is low; odd bits (DA1) when CLKOUT+ is high - reduces pin count by 2×. |
| DB12_13+ / DB12_13– (Pins 38,39) | DDR LVDS output, Channel B bits 12–13 | Final data pair for Channel B; supports 100Ω on-chip termination and 1.75mA/3.5mA programmable drive strength. |
| CLKOUT+/CLKOUT– (Pins 40,41) | DDR data clock output | Synchronizes all LVDS data outputs; phase delay programmable via SPI to align with FPGA capture timing. |
| PAR/SER (Pin 63) | Programming mode select | Ground = serial SPI mode (full configuration); VDD = parallel mode (limited control via CS/SCK/SDI pins). |
Key Features
| Feature | Design Value |
|---|---|
| Dual simultaneous-sampling ADC cores | Ensures precise channel-to-channel phase matching (<1ps skew) critical for MIMO and beamforming systems. |
| DDR LVDS output interface | Reduces I/O count by 50% vs. single-data-rate, easing FPGA routing and lowering EMI in high-density RF boards. |
| Programmable LVDS output current | Supports 1.75mA (lower power, shorter traces) or 3.5mA (longer traces, higher noise immunity) without external resistors. |
| On-chip 100Ω differential termination | Eliminates need for external termination resistors on each LVDS pair, saving board space and improving signal integrity. |
| 6-cycle deterministic pipeline latency | Enables predictable timing closure in real-time DSP pipelines, such as digital downconverters or adaptive filters. |
| Low-power Nap and Sleep modes | Nap mode draws 198mW while preserving configuration; Sleep mode draws <5mW - ideal for burst-mode or TDD systems. |
Applications
| Cellular Basestation Receiver | Software-Defined Radio (SDR) |
|---|---|
Use Scenario: Digitizing 20MHz LTE carriers centered at 2.6GHz using IF sampling at 184MHz. IC Role / Device Role / Timing Role: Dual-channel ADC performing simultaneous I/Q sampling with matched gain/phase for coherent demodulation. Use Value: 90dB SFDR suppresses adjacent-channel interference; 1.25GHz bandwidth avoids external anti-alias filtering. |
Use Scenario: Wideband spectrum monitoring from 100MHz to 2GHz with real-time FFT analysis. IC Role / Device Role / Timing Role: High-speed digitizer feeding FPGA-based digital frontend with deterministic 6-cycle latency. Use Value: 70dB SNR enables detection of –120dBm signals; DDR LVDS simplifies interface to Xilinx Kintex-7 transceivers. |
| Medical Ultrasound Beamformer | High-Speed Test & Measurement |
Use Scenario: Sampling 15MHz echo return signals from phased-array transducers with >100dB dynamic range. IC Role / Device Role / Timing Role: Precision dual ADC capturing time-aligned channel data for digital beam steering and focusing. Use Value: ±0.85LSB INL preserves image linearity; low 1.82LSBRMS transition noise minimizes speckle artifacts. |
Use Scenario: Real-time oscilloscope frontend capturing transient RF events at 210Msps with deep memory buffer. IC Role / Device Role / Timing Role: High-fidelity digitizer providing calibrated amplitude accuracy and low harmonic distortion. Use Value: 90dB SFDR ensures clean fundamental representation; 616mW power enables fanless portable design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9680BCPZ-500 | Higher 500Msps sampling rate, JESD204B interface, 75dB SNR, 1.25W power | Targets wider instantaneous bandwidths and FPGA JESD204B integration; not pin-compatible | Select for systems needing >250MHz instantaneous bandwidth or JESD204B backhaul; requires redesign of clocking and layout. |
| LTC2155IUP-14#PBF | Same family, 170Msps max, 567mW power, identical pinout and register map | Lower speed/power trade-off for cost- and thermally-constrained designs | Select for applications where 170Msps suffices (e.g., narrowband wireless or lower IF frequencies) to reduce power and thermal load. |
Compared with AD9680BCPZ-500, the LTC2156IUP-14#PBF offers lower power and simpler LVDS interfacing but lacks JESD204B; compared with LTC2155IUP-14#PBF, it delivers 40Msps higher throughput at only 49mW additional power - making it optimal for mid-tier SDR and basestation upgrades.
Availability
LTC2156IUP-14#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio, and medical ultrasound systems requiring stable component supply across extended temperature ranges (–40°C to +85°C) and long production lifecycles.
Supply support for LTC2156IUP-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets.
The LTC2156IUP-14#PBF belongs to Linear's high-speed ADC product line, designed specifically for demanding RF/IF digitization in communications infrastructure where dynamic range, low latency, and thermal efficiency are critical.
FAQ
What is the maximum sampling rate supported by the LTC2156IUP-14#PBF?
The LTC2156IUP-14#PBF supports a maximum sampling rate of 210Msps across both channels simultaneously. This is specified under recommended operating conditions (VDD = OVDD = 1.8V, fSAMPLE ≤ 210MHz), with guaranteed AC performance including 70dB SNR and 90dB SFDR at this rate. Operation above 210Msps is not characterized and may degrade INL, DNL, or SFDR.
Does the LTC2156IUP-14#PBF support internal or external voltage reference operation?
Yes, the LTC2156IUP-14#PBF supports both internal and external reference modes. Connecting SENSE to VDD selects the internal 1.25V reference and ±0.75V input range; applying 1.20V–1.30V to SENSE selects external reference mode with ±0.6 × VSENSE input range. VREF pin outputs the internal reference voltage and must be bypassed with a 2.2µF capacitor.
How many LVDS data pairs does the LTC2156IUP-14#PBF provide per channel?
The LTC2156IUP-14#PBF provides seven differential LVDS output pairs per channel: DA0_1 through DA12_13 for Channel A and DB0_1 through DB12_13 for Channel B. Each pair carries two multiplexed data bits (even/odd) synchronized to CLKOUT+, delivering full 14-bit resolution per channel in DDR format.
What is the purpose of the PAR/SER pin on the LTC2156IUP-14#PBF?
The PAR/SER pin (Pin 63) selects the programming interface mode: grounded for serial SPI mode (full register access via CS/SCK/SDI/SDO), or tied to VDD for parallel mode (limited control via CS/SCK/SDI only). In parallel mode, SCK triggers Sleep mode and SDI selects LVDS current; SPI readback is disabled.
Is the LTC2156IUP-14#PBF pin-compatible with other members of the LTC215X-14 family?
Yes, the LTC2156IUP-14#PBF is pin-compatible with LTC2157-14 and LTC2155-14 variants in the same 64-pin QFN package. All share identical pin functions, power domains, and register maps - allowing drop-in replacement with only speed and power adjustments (250Msps/650mW for LTC2157, 170Msps/567mW for LTC2155).
LTC2156IUP-14#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 210M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-QFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2156IUP-14#PBF FAQ
1.How can I place an order for LTC2156IUP-14#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2156IUP-14#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2156IUP-14#PBF reliable?
The price and inventory of LTC2156IUP-14#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2156IUP-14#PBF is usually 5 days.
3.What payment methods are accepted for LTC2156IUP-14#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2156IUP-14#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2156IUP-14#PBF?
LTC2156IUP-14#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2156IUP-14#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2156IUP-14#PBF?
For technical support, including LTC2156IUP-14#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2156IUP-14#PBF requirements.
6.How does Aetrix verify that LTC2156IUP-14#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2156IUP-14#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2156IUP-14#PBF meets industry standards.
7.What is the process for return or replacement of LTC2156IUP-14#PBF?
All LTC2156IUP-14#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2156IUP-14#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2156IUP-14#PBF part is unused and in its original packaging.
Return procedure for LTC2156IUP-14#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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