Analog Devices Inc. LTC2159IUK#PBF
- Part No.:
- LTC2159IUK#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LTC2159IUK#PBF.pdf
- Description:
- IC ADC 16BIT PIPELINED 48QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2159IUK#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, 20Msps low-power analog-to-digital converter optimized for high-frequency, wide-dynamic-range signal digitization in communications systems. It delivers 77dB SNR, 90dB SFDR, and ultralow 0.07psRMS jitter, enabling high-fidelity undersampling of IF signals up to 550MHz full-power bandwidth. Its single 1.8V supply, selectable CMOS/DDR-CMOS/DDR-LVDS outputs, and –40°C to +85°C industrial temperature range make it suitable for cellular base stations and portable medical imaging.
For engineers reviewing the LTC2159IUK#PBF datasheet, LTC2159IUK#PBF pinout, LTC2159IUK#PBF application, or LTC2159IUK#PBF equivalent, key selection considerations include its differential input architecture with 1–2VP-P range selection, SPI-configurable clock duty cycle stabilizer, optional data randomizer, and support for shutdown/nap modes to manage system-level power integrity in multichannel SDR and data acquisition designs.
Technical Context
The LTC2159IUK#PBF employs a pipeline ADC architecture with integrated sample-and-hold and correction logic, supporting both single-ended and differential encode inputs (ENC+/ENC–) across PECL/LVDS/TTL/CMOS logic families. Its internal 1.25V reference and external reference mode (via SENSE pin) allow flexible input range scaling from ±0.5V to ±1.0V, while VCM output (nominally VDD/2) provides precise common-mode biasing for differential analog inputs.
Digital interface flexibility includes full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS output modes - each with programmable output swing (1.2–1.8V for CMOS) or current levels (1.75mA/3.5mA for LVDS). The SPI port enables real-time configuration of features including clock duty cycle stabilization, data randomization, and power management modes without requiring external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in precision measurement applications. |
| Sampling Rate | 20Msps maximum - supports real-time digitization of wideband IF signals in software-defined radio front ends. |
| SNR / SFDR | 77dB SNR and 90dB SFDR at 30MHz input - enables high-fidelity capture of weak signals adjacent to strong interferers in cellular infrastructure. |
| Jitter Performance | 0.07psRMS sampling jitter - minimizes aperture uncertainty, critical for undersampling >100MHz IF frequencies with low noise floor degradation. |
| Power Consumption | 43mW at 20Msps with CMOS outputs - achieves ultra-low power per bit (2.69µW/bit) for battery-constrained portable imaging systems. |
| Analog Input Bandwidth | 550MHz full-power bandwidth - accommodates direct RF sampling of L-band and S-band signals without external amplification. |
| INL / DNL | ±2LSB INL (typ), ±0.5LSB DNL (typ) - ensures accurate amplitude linearity for calibrated instrumentation and spectral analysis. |
Pinout & Package
Package: 48-lead (7mm × 7mm) plastic QFN with exposed thermal pad (Pin 49 = GND, must be soldered to PCB ground plane).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCM (Pin 1) | Common-mode bias output | Nominally VDD/2 (0.9V); used to set optimal DC level for differential analog inputs - requires 0.1µF ceramic bypass to GND. |
| AIN+, AIN– (Pins 2, 3) | Differential analog input pair | Accepts 1–2VP-P differential signal centered on VCM; 550MHz bandwidth supports direct IF sampling without external amplifiers. |
| ENC+, ENC– (Pins 15, 16) | Differential encode clock inputs | Trigger conversion on rising/falling edges; supports single-ended mode (ENC– tied to GND) to reduce system clock driver complexity. |
| PAR/SER (Pin 9) | Programming mode select | Ground = serial SPI interface (CS/SCK/SDI/SDO active); VDD = parallel control mode - determines functional scope of digital configuration pins. |
| D0–D15 / DDR variants (Pins 21–40) | Digital data outputs | Configurable as full-rate CMOS, DDR-CMOS (8 pins), or DDR-LVDS (8 differential pairs) - reduces I/O count and EMI in dense PCB layouts. |
| CLKOUT+, CLKOUT– (Pins 30, 29) | Data output clock | Synchronizes digital output transitions; phase delay programmable via SPI to align with FPGA/ASIC capture timing requirements. |
| SENSE (Pin 46) | Reference programming input | Selects input range: tie to VDD → ±1V (2VP-P), tie to GND → ±0.5V (1VP-P), apply 0.625–1.3V → ±0.8×VSENSE - enables dynamic range optimization per signal chain. |
Key Features
| Feature | Design Value |
|---|---|
| Ultralow jitter sampling | 0.07psRMS enables clean undersampling of 100+ MHz IF signals without SNR penalty - essential for zero-IF and direct-conversion receivers. |
| Selectably programmable output interface | Runtime-switchable between CMOS, DDR-CMOS, and DDR-LVDS via SPI - allows hardware reuse across cost-sensitive (CMOS) and noise-critical (LVDS) system variants. |
| Integrated clock duty cycle stabilizer | Compensates for asymmetric clock waveforms from PLLs or crystal oscillators - maintains full AC performance without external duty cycle correction circuitry. |
| Low-power operational modes | 1mW sleep mode and 10mW nap mode enable rapid power-state transitions - ideal for time-sliced radar or burst-mode communication systems. |
| Flexible reference and input range control | SENSE pin configures ±0.5V to ±1.0V input range; internal 1.25V reference eliminates need for external voltage reference IC in space-constrained designs. |
Applications
| Cellular Base Stations | Software Defined Radios |
|---|---|
Use Scenario: Digitizing 70–250MHz IF signals from multi-carrier GSM/UMTS/LTE transceivers in macrocell and small cell radios. IC Role / Device Role / Timing Role: High-linearity, low-jitter ADC capturing wide instantaneous bandwidth for digital predistortion and MIMO channel estimation. Use Value: 90dB SFDR prevents intermodulation distortion from masking adjacent-channel interference, directly improving ACLR compliance and spectral efficiency. | Use Scenario: Reconfigurable RF front end in military/commercial SDR platforms requiring simultaneous multi-band reception and agile frequency hopping. IC Role / Device Role / Timing Role: Primary ADC in FPGA-based receiver chain, interfacing via DDR-LVDS to minimize routing congestion and crosstalk in high-speed PCBs. Use Value: 550MHz analog bandwidth and 20Msps sampling support real-time capture of 10MHz instantaneous bandwidth across HF/VHF/UHF bands without tunable filters. |
| Portable Medical Imaging | Multichannel Data Acquisition |
Use Scenario: Ultrasound beamforming subsystem digitizing echo return signals from phased-array transducers in handheld diagnostic devices. IC Role / Device Role / Timing Role: Low-power, high-SNR ADC operating from single 1.8V supply to extend battery life while preserving image contrast resolution. Use Value: 43mW power consumption at 20Msps enables integration of 8–16 channels within thermal limits of compact enclosures, reducing cooling overhead. | Use Scenario: Precision test equipment capturing transient waveforms from sensors (strain gauges, accelerometers) in industrial condition monitoring systems. IC Role / Device Role / Timing Role: High-accuracy ADC with ±2LSB INL ensuring traceable measurement linearity across temperature for ISO/IEC 17025 calibration compliance. Use Value: SPI-configurable nap mode allows synchronized power gating across multiple LTC2159IUK#PBF units during idle periods - cutting system-level standby power by >80%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9268BCPZ-20 | 16-bit, 20Msps, but uses 3.3V/1.8V dual supply; higher 125mW power; no integrated clock stabilizer. | Requires external duty cycle correction and level-shifting for 1.8V logic domains; less suitable for ultra-low-power portable systems. | Prefer when legacy 3.3V digital interfaces exist and jitter tolerance is relaxed beyond 0.1psRMS. |
| ADS52J90IRGCT | 16-bit, 20Msps, JESD204B serial output; 1.25V/1.8V supplies; 110mW typical power; no CMOS/DDR-CMOS option. | Eliminates parallel bus routing but adds FPGA JESD204B IP complexity; incompatible with simple microcontroller or ASIC parallel capture. | Prefer when high channel density (>8 channels) and deterministic latency matter more than board-level simplicity and power budget. |
Compared with AD9268BCPZ-20 and ADS52J90IRGCT, the LTC2159IUK#PBF uniquely combines single-supply operation, sub-50mW power, integrated clock conditioning, and flexible parallel output modes - making it optimal for thermally constrained, cost-sensitive, and layout-simple embedded RF digitization where JESD204B infrastructure is unavailable.
Availability
LTC2159IUK#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, portable medical imaging, software-defined radio, and multichannel data acquisition requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC2159IUK#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2159IUK#PBF belongs to ADI's high-speed precision ADC product line, engineered specifically for demanding communications and instrumentation applications where low power, high dynamic range, and robust timing performance are non-negotiable design requirements.
FAQ
What is the operating temperature range of the LTC2159IUK#PBF?
The LTC2159IUK#PBF is rated for industrial operation from –40°C to +85°C, as indicated by the "I" grade suffix in the part number. This range is validated across all electrical specifications including SNR, SFDR, INL, and power consumption - ensuring reliable performance in outdoor base stations, field-deployable medical devices, and factory-floor data loggers without derating.
Does the LTC2159IUK#PBF require an external reference voltage?
No, the LTC2159IUK#PBF includes an internal 1.25V bandgap reference and supports both internal and external reference modes. When SENSE is tied to VDD or GND, the internal reference sets ±1V or ±0.5V input range respectively. An external reference (0.625–1.3V) applied to SENSE selects ±0.8×VSENSE range - eliminating need for external reference ICs in most implementations.
How does the clock duty cycle stabilizer in the LTC2159IUK#PBF improve system performance?
The clock duty cycle stabilizer in the LTC2159IUK#PBF corrects asymmetric encode clock waveforms (e.g., from crystal oscillators or PLLs with >60% duty cycle error), maintaining full 77dB SNR and 90dB SFDR at 20Msps. Without it, duty cycle distortion would degrade aperture jitter and increase harmonic distortion - particularly critical in undersampling architectures where clock purity directly impacts IF signal fidelity.
Can the LTC2159IUK#PBF interface directly with an FPGA using LVDS signaling?
Yes, the LTC2159IUK#PBF supports double-data-rate LVDS output mode with programmable 1.75mA or 3.5mA current drive and optional on-chip 100Ω termination per differential pair. Its CLKOUT+/CLKOUT– outputs provide source-synchronous timing aligned to data transitions, enabling direct connection to Xilinx Artix-7 or Intel Cyclone V FPGA LVDS input banks without external terminations or level shifters.
What power savings does the nap mode provide for the LTC2159IUK#PBF?
The nap mode reduces LTC2159IUK#PBF power consumption to 10mW - an 80% reduction versus its 43mW active operation at 20Msps. In this state, the ADC retains register settings and reference biasing while disabling the sample-and-hold and core conversion circuitry, enabling fast wake-up (<1µs) for burst-mode acquisition in radar or time-of-flight sensing applications.
LTC2159IUK#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 20M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 48-QFN (7x7)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2159IUK#PBF FAQ
1.How can I place an order for LTC2159IUK#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2159IUK#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2159IUK#PBF reliable?
The price and inventory of LTC2159IUK#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2159IUK#PBF is usually 5 days.
3.What payment methods are accepted for LTC2159IUK#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2159IUK#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2159IUK#PBF?
LTC2159IUK#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2159IUK#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2159IUK#PBF?
For technical support, including LTC2159IUK#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2159IUK#PBF requirements.
6.How does Aetrix verify that LTC2159IUK#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2159IUK#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2159IUK#PBF meets industry standards.
7.What is the process for return or replacement of LTC2159IUK#PBF?
All LTC2159IUK#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2159IUK#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2159IUK#PBF part is unused and in its original packaging.
Return procedure for LTC2159IUK#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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