Analog Devices Inc. LTC2160CUK#PBF
- Part No.:
- LTC2160CUK#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LTC2160CUK#PBF.pdf
- Description:
- IC ADC 16BIT PIPELINED 48QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2160CUK#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, 25Msps low-power analog-to-digital converter optimized for high-dynamic-range signal digitization in communications and instrumentation systems. It delivers 77dB SNR, 90dB SFDR, and ultralow 0.07psRMS jitter at 25Msps sampling rate, with ±2LSB INL and ±0.5LSB DNL - enabling precise undersampling of IF signals up to 140MHz in cellular base station receivers.
For engineers reviewing the LTC2160CUK#PBF datasheet, LTC2160CUK#PBF pinout, LTC2160CUK#PBF application, or LTC2160CUK#PBF equivalent, this page provides verified package mapping (48-lead 7mm × 7mm QFN), confirmed CMOS/LVDS output mode support, validated clock input flexibility (differential or single-ended), and real-world performance data across temperature (0°C to 70°C).
Technical Context
The LTC2160CUK#PBF implements a fully differential sample-and-hold front-end with 550MHz full-power bandwidth and supports internal/external reference selection via SENSE pin. Its digital interface offers three configurable output modes - full-rate CMOS, DDR CMOS, or DDR LVDS - each with independent OVDD supply (1.1V–1.8V) and on-chip termination for LVDS.
Configuration is handled via SPI serial port (CS/SCK/SDI/SDO) or parallel logic inputs depending on PAR/SER pin state. Optional features include clock duty cycle stabilizer, data output randomizer, and low-power Nap (10mW) and Sleep (1mW) modes - all controllable without external firmware overhead.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in precision measurement systems. |
| Sampling Rate | 25Msps - matches mid-bandwidth applications like portable medical imaging and multichannel DAQ where power efficiency outweighs ultra-high speed. |
| SNR / SFDR | 77dB SNR and 90dB SFDR at 70MHz input - enables clean digitization of narrowband RF signals with minimal noise floor elevation. |
| Power Dissipation | 45mW typical at 25Msps with 1.8V supplies - reduces thermal load and simplifies PCB layout in space-constrained embedded designs. |
| Analog Input Range | Selectable 1VP-P to 2VP-P differential range - allows optimization for signal amplitude while maintaining 77dB SNR across full scale. |
| Jitter Performance | 0.07psRMS encode jitter - limits aperture uncertainty to <0.05% of LSB at 70MHz, critical for undersampling architectures. |
| Operating Temperature | 0°C to 70°C (Commercial grade) - validated for industrial control, test equipment, and non-automotive embedded platforms. |
Pinout & Package
48-lead (7mm × 7mm) plastic QFN package with exposed thermal pad (Pin 49 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCM (1) | Common-mode bias output | Provides stable VDD/2 reference (±25mV) to bias AIN+/AIN–; must be bypassed with 0.1µF capacitor to GND. |
| AIN+ / AIN– (2,3) | Differential analog input | Accepts 1–2VP-P differential signal; CMRR = 80dB ensures rejection of common-mode noise in noisy environments. |
| ENC+ / ENC– (15,16) | Encode clock inputs | Support differential (LVDS/PECL) or single-ended (TTL/CMOS) drive; falling edge on ENC– triggers conversion when used differentially. |
| PAR/SER (9) | Programming mode select | Hardwired to GND for SPI configuration or VDD for parallel control - not logic-driven; determines function of CS/SCK/SDI/SDO pins. |
| D0–D15 (21–24,36–40) | Parallel data outputs | Configurable as full-rate CMOS, DDR CMOS, or DDR LVDS; output swing set by OVDD (1.1–1.8V) with on-chip 100Ω LVDS termination. |
| VDD (12,13,47,48) | Analog supply | 1.7–1.9V supply with separate bypassing per pin group; total IVDD = 25.4mA typical at 25Msps. |
| OVDD (32) | Digital output supply | Independent 1.1–1.9V rail for output drivers - enables level-shifting to match FPGA or ASIC I/O voltage requirements. |
Key Features
| Feature | Design Value |
|---|---|
| Ultralow encode jitter | 0.07psRMS enables accurate undersampling of IF signals up to 140MHz without significant SNR degradation. |
| Flexible output interface | Hardware-selectable CMOS, DDR CMOS, or DDR LVDS outputs reduce need for external level translators or serializers. |
| Low-power operating modes | Nap (10mW) and Sleep (1mW) states allow rapid power-state transitions during idle periods in battery-powered instruments. |
| Configurable input range | 1VP-P to 2VP-P differential range selection optimizes dynamic range usage for varying signal amplitudes without external gain stages. |
| Integrated clock conditioning | Optional duty cycle stabilizer maintains >45%–55% encode clock symmetry even with distorted input clocks, preserving timing margin. |
Applications
| Cellular Base Station Receiver | Portable Medical Ultrasound |
|---|---|
|
Use Scenario: Digitizing 70MHz IF signals from quadrature demodulators in LTE femtocell transceivers. IC Role / Device Role / Timing Role: High-fidelity ADC capturing complex baseband waveforms with 77dB SNR and 90dB SFDR to preserve EVM and ACLR metrics. Use Value: Enables direct IF sampling architecture, eliminating multiple analog downconversion stages and reducing BOM count by 3+ components. |
Use Scenario: Acquiring echo return signals from piezoelectric transducers in handheld ultrasound scanners. IC Role / Device Role / Timing Role: Low-noise, low-power ADC converting 5–15MHz analog beamformed signals with minimal added quantization noise. Use Value: 45mW power consumption extends battery life beyond 4 hours per charge while maintaining diagnostic image resolution. |
| Multichannel Data Acquisition | Nondestructive Testing (NDT) |
|
Use Scenario: Simultaneous sampling of 8–16 sensor channels in industrial vibration monitoring systems. IC Role / Device Role / Timing Role: Precision ADC providing synchronized 16-bit samples across channels with <10ps inter-channel skew in DDR LVDS mode. Use Value: Eliminates need for external synchronization circuitry and supports deterministic timestamping of transient events. |
Use Scenario: Capturing high-frequency acoustic emissions from turbine blades during ultrasonic inspection. IC Role / Device Role / Timing Role: Wideband ADC digitizing 100kHz–10MHz pulse echoes with 550MHz S/H bandwidth to preserve rise-time fidelity. Use Value: Resolves sub-micron crack signatures in FFT-based defect analysis due to low 3.2LSBRMS transition noise. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-resolution, medium-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9265BCPZ-25 | 16-bit, 25Msps; requires external reference and has higher 65mW power; no integrated duty cycle stabilizer. | Used in military/aerospace DAQ where extended temperature range (–40°C to +85°C) is mandatory. | Choose AD9265BCPZ-25 only if external reference control or MIL-STD-883 qualification is required. |
| ADS52J90IRGCT | 16-bit, 25Msps; includes JESD204B interface and on-chip decimation filters; consumes 120mW. | Targeted at high-channel-count systems needing serialized backhaul to FPGAs with reduced PCB trace count. | Choose ADS52J90IRGCT only when JESD204B compatibility and digital filtering offload are design priorities. |
Compared with AD9265BCPZ-25 and ADS52J90IRGCT, the LTC2160CUK#PBF provides superior power efficiency (45mW vs ≥65mW), integrated clock conditioning, and simpler board-level implementation - making it optimal for cost-sensitive, thermally constrained commercial instrumentation.
Availability
LTC2160CUK#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, portable medical imaging, and multichannel data acquisition requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production lots.
Supply support for LTC2160CUK#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance signal chain portfolio, emphasizing precision analog, RF, and mixed-signal ICs for demanding measurement and communication applications.
The LTC2160CUK#PBF belongs to the LTC216x family of ultralow-jitter, low-power ADCs designed specifically for communications infrastructure, portable instrumentation, and high-fidelity data acquisition where SNR, SFDR, and power efficiency are co-optimized.
FAQ
What is the maximum analog input frequency supported by the LTC2160CUK#PBF?
The LTC2160CUK#PBF features a 550MHz full-power bandwidth sample-and-hold amplifier, allowing accurate digitization of analog inputs up to 140MHz while maintaining 77dB SNR and 90dB SFDR. This makes the LTC2160CUK#PBF suitable for undersampling IF signals in software-defined radio and base station receiver applications.
Does the LTC2160CUK#PBF support both internal and external voltage references?
Yes, the LTC2160CUK#PBF supports both internal and external reference configurations. When using the internal reference, VREF outputs 1.250V ±25ppm/°C; for external reference mode, the SENSE pin accepts 0.625V–1.300V, enabling system-level reference sharing and improved channel-to-channel matching in multichannel systems using the LTC2160CUK#PBF.
Can the LTC2160CUK#PBF operate with a single 1.8V supply?
Yes, the LTC2160CUK#PBF operates from a single 1.8V analog supply (VDD = 1.7V–1.9V) and a separate 1.1V–1.8V digital output supply (OVDD). This dual-supply architecture allows independent optimization of analog performance and I/O compatibility - for example, running VDD at 1.8V for best SNR while setting OVDD to 1.2V to interface with low-voltage FPGAs, all within the specified operation of the LTC2160CUK#PBF.
What digital output interfaces does the LTC2160CUK#PBF support?
The LTC2160CUK#PBF supports three digital output modes: full-rate CMOS, double-data-rate (DDR) CMOS, and DDR LVDS - selected via PAR/SER pin and SPI register settings. DDR LVDS mode includes on-chip 100Ω termination and supports 100Ω differential loads, reducing external component count and improving signal integrity over longer traces compared to standard CMOS outputs on the LTC2160CUK#PBF.
Is the LTC2160CUK#PBF pin-compatible with other members of the LTC216x family?
No, the LTC2160CUK#PBF is not pin-compatible with LTC2161CUK#PBF or LTC2162CUK#PBF. Although all share the same 48-lead QFN package and pinout numbering, the digital output pin assignments differ significantly between speed grades - e.g., D0–D15 are single-ended in LTC2160CUK#PBF CMOS mode but paired as differential LVDS pairs (D0_1+, D0_1–, etc.) in LTC2160CUK#PBF LVDS mode - requiring unique PCB layouts per variant.
LTC2160CUK#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 25M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 48-QFN (7x7)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2160CUK#PBF FAQ
1.How can I place an order for LTC2160CUK#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2160CUK#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2160CUK#PBF reliable?
The price and inventory of LTC2160CUK#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2160CUK#PBF is usually 5 days.
3.What payment methods are accepted for LTC2160CUK#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2160CUK#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2160CUK#PBF?
LTC2160CUK#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2160CUK#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2160CUK#PBF?
For technical support, including LTC2160CUK#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2160CUK#PBF requirements.
6.How does Aetrix verify that LTC2160CUK#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2160CUK#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2160CUK#PBF meets industry standards.
7.What is the process for return or replacement of LTC2160CUK#PBF?
All LTC2160CUK#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2160CUK#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2160CUK#PBF part is unused and in its original packaging.
Return procedure for LTC2160CUK#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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