Analog Devices Inc. LTC2172IUKG-12#PBF
- Part No.:
- LTC2172IUKG-12#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 52-WFQFN Exposed Pad
- Datasheet:
-
LTC2172IUKG-12#PBF.pdf
- Description:
- IC ADC 12BIT PIPELINED 52QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2172IUKG-12#PBF from Analog Devices (acquired Linear Technology) is a 12-bit, 4-channel simultaneous-sampling analog-to-digital converter optimized for high-frequency communications signal digitization. It delivers 71dB SNR, 90dB SFDR, and 0.15psRMS jitter at 65Msps sampling rate, with full-power bandwidth of 800MHz and ±0.3LSB INL (typ). It operates from a single 1.8V supply and targets IF undersampling in cellular base stations and software-defined radios.
For engineers reviewing the LTC2172IUKG-12#PBF datasheet, LTC2172IUKG-12#PBF pinout, LTC2172IUKG-12#PBF application, or LTC2172IUKG-12#PBF equivalent, key selection criteria include guaranteed 65Msps operation with serial LVDS outputs, differential input support up to 2VP-P, internal clock duty cycle stabilization, and industrial temperature range (–40°C to +85°C) compliance.
Technical Context
The LTC2172IUKG-12#PBF implements four independent 12-bit ADC cores with shared sample-and-hold and integrated 800MHz bandwidth front-end. Its ultralow jitter enables clean undersampling of IF signals up to 140MHz while maintaining 71dB SNR at 70MHz input. The architecture supports both 1-lane and 2-lane serial LVDS output modes with programmable current drive (1.75mA/3.5mA) and on-chip 100Ω termination.
It features dual reference paths (internal 1.25V VREF ±25ppm/°C or external SENSE pin), SPI-configurable power modes (Nap: 75mW, Sleep: 1mW), and flexible encode interface accepting differential (LVDS/PECL) or single-ended (CMOS/TTL) clocks. Channel-to-channel crosstalk is –90dBc (near) and –105dBc (far), ensuring integrity in multichannel acquisition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in demanding measurement systems. |
| Sampling Rate | 65Msps maximum - enables real-time digitization of wideband IF signals up to 140MHz without aliasing in undersampling architectures. |
| SNR / SFDR | 71dB / 90dB at 70MHz input - provides high dynamic range for detecting weak signals adjacent to strong interferers in SDR and base station receivers. |
| Jitter | 0.15psRMS aperture jitter - directly limits SNR degradation at high input frequencies; enables >10-bit ENOB at 100MHz. |
| Power Consumption | 306mW total at 65Msps, 2-lane LVDS - balances performance and thermal budget in dense RF front-end modules. |
| Analog Input Range | Selectable 1VP-P to 2VP-P differential - simplifies interface design with transformer-coupled or amplifier-driven inputs across multiple gain stages. |
| Operating Temperature | –40°C to +85°C (Industrial grade) - validated for deployment in outdoor base station enclosures and portable medical imaging equipment. |
Pinout & Package
52-pin (7mm × 8mm) plastic QFN package with exposed thermal pad (Pin 53 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1+ / AIN1– (Pins 1, 2) | Channel 1 differential analog input | Accepts 1–2VP-P differential signal; common-mode biased by VCM12 (Pin 3) at ~0.9V. |
| ENC+ / ENC– (Pins 17, 18) | Differential encode clock input | Triggers conversion on both edges; supports duty cycle stabilization for non-50% clocks. |
| OUT1A+/OUT1A– (Pins 41–44) | Channel 1 serial LVDS data output (lane A) | Delivers serialized 12/14/16-bit data; configurable 1.75mA or 3.5mA drive strength. |
| DCO+ / DCO– (Pins 27, 28) | Data clock output (LVDS) | Synchronizes LVDS data stream; phase-aligned to sampled data with <1ns skew. |
| FR+ / FR– (Pins 29, 30) | Frame clock output (LVDS) | Indicates start of new conversion frame; period equals 4× DCO period in 4-channel mode. |
| SDO (Pin 46) | Serial data output / termination control | In serial mode: readback of configuration registers; in parallel mode: enables internal 100Ω LVDS terminations. |
Key Features
| Feature | Design Value |
|---|---|
| Simultaneous 4-channel sampling | Eliminates inter-channel timing skew (<1ps), enabling coherent beamforming and I/Q channel matching in phased-array systems. |
| Programmable LVDS serialization | Supports 1-lane (12/14/16-bit) or 2-lane (12/14/16-bit) output modes - reduces PCB trace count and EMI vs parallel interfaces. |
| Internal clock duty cycle stabilizer | Allows use of asymmetric clocks (e.g., from PLLs or dividers) without SNR degradation - removes need for external duty-cycle correction circuitry. |
| Low-power Nap and Sleep modes | Nap mode draws 75mW; Sleep mode draws 1mW - enables rapid power-state transitions in battery-powered or burst-mode SDR applications. |
| Flexible reference options | Internal 1.25V reference (±25ppm/°C) or external SENSE pin (0.625–1.3V) - supports precision calibration and ratiometric sensor interfacing. |
Applications
| Cellular Base Stations | Software Defined Radios |
|---|---|
|
Use Scenario: Digitizing 70–140MHz IF signals from multi-carrier LTE/5G transceivers with high adjacent-channel rejection requirements. IC Role / Device Role / Timing Role: Primary quadrature ADC for direct-conversion receiver chains, providing synchronized I/Q sampling with <1ps inter-channel skew. Use Value: 90dB SFDR ensures detection of low-level user signals amid strong interferers; 0.15psRMS jitter preserves ENOB above 10 bits at 100MHz. |
Use Scenario: Reconfigurable RF front-end in field-deployable spectrum analyzers and cognitive radio platforms requiring wide instantaneous bandwidth. IC Role / Device Role / Timing Role: High-speed data acquisition engine supporting real-time FFT processing and adaptive filtering across 200MHz+ instantaneous bandwidth. Use Value: 65Msps sampling with 800MHz input BW enables 100MHz real-time analysis span; serial LVDS minimizes FPGA pin count and layout complexity. |
| Portable Medical Imaging | Multichannel Data Acquisition |
|
Use Scenario: Ultrasound beamformer digitizing echo returns from 64+ transducer elements with precise time-of-flight alignment. IC Role / Device Role / Timing Role: Simultaneous-sampling ADC for coherent channel combining; low INL (±0.3LSB) ensures accurate amplitude reconstruction. Use Value: 71dB SNR enables detection of subtle tissue boundaries; industrial temp range supports operation in battery-powered handheld scanners. |
Use Scenario: High-fidelity vibration monitoring in industrial predictive maintenance systems capturing transient mechanical events across multiple sensors. IC Role / Device Role / Timing Role: Precision multichannel digitizer for synchronized capture of acceleration, temperature, and acoustic emission signals. Use Value: ±0.1LSB DNL (typ) prevents histogram distortion in spectral analysis; shutdown mode reduces system standby power by >99%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 12-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9257BSTZ-65 | 65Msps, 14-bit, 4-channel, JESD204B output; higher resolution but larger 72-lead LFCSP package and 1.25V/2.5V dual supplies. | Better ENOB for DC-critical instrumentation; unsuitable for space-constrained 7×8mm QFN layouts or single-supply designs. | Choose AD9257BSTZ-65 when 14-bit resolution and JESD204B backplane integration outweigh size and supply complexity. |
| LTC2171IUKG-12#PBF | Same pinout and feature set, but rated for 40Msps max sampling rate and lower power (198mW total). | Valid drop-in replacement where 40Msps suffices; not suitable for 65Msps IF sampling or 140MHz input bandwidth requirements. | Choose LTC2171IUKG-12#PBF for cost-sensitive, lower-bandwidth applications where full 65Msps capability is unnecessary. |
Compared with AD9257BSTZ-65, the LTC2172IUKG-12#PBF offers smaller footprint and single-supply simplicity at the expense of resolution and digital interface flexibility; compared with LTC2171IUKG-12#PBF, it delivers 65Msps performance with identical pinout and industrial temperature rating.
Availability
LTC2172IUKG-12#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio development, and portable medical imaging systems requiring stable component supply across extended product lifecycles.
Supply support for LTC2172IUKG-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2172IUKG-12#PBF belongs to ADI's high-speed data converter product line, designed specifically for demanding communications applications requiring simultaneous multichannel sampling, low jitter, and robust AC performance across wide input bandwidths.
FAQ
What is the maximum sampling rate supported by the LTC2172IUKG-12#PBF?
The LTC2172IUKG-12#PBF supports a maximum sampling rate of 65Msps, as confirmed in the Absolute Maximum Ratings and Timing Characteristics tables. This rate is validated across the full industrial temperature range (–40°C to +85°C) and enables digitization of input signals up to 140MHz using undersampling techniques. Operation above 65Msps is not specified and may compromise AC performance metrics such as SNR and SFDR.
Does the LTC2172IUKG-12#PBF support single-ended clock inputs?
Yes, the LTC2172IUKG-12#PBF supports single-ended clock inputs via the ENC+ pin (Pin 17) with ENC– tied to GND, as documented in the Digital Inputs And Outputs section. In this mode, ENC+ accepts CMOS/TTL logic levels (VIH = 1.2V, VIL = 0.6V at VDD = 1.8V), and the internal duty cycle stabilizer remains active to maintain performance with non-50% duty cycle clocks.
What are the LVDS output configuration options for the LTC2172IUKG-12#PBF?
The LTC2172IUKG-12#PBF supports two LVDS serialization modes: 1-lane (one bit per channel per DCO edge) and 2-lane (two bits per channel per DCO edge), selected via the CS pin. Output current is configurable to 1.75mA or 3.5mA using the SCK pin, and on-chip 100Ω termination can be enabled via the SDO pin in parallel programming mode - all without external components.
Can the LTC2172IUKG-12#PBF operate with an external reference voltage?
Yes, the LTC2172IUKG-12#PBF supports external reference operation via the SENSE pin (Pin 32), which accepts 0.625V to 1.300V. When used, the internal 1.25V reference is disabled, and the ADC full-scale range scales linearly with the applied SENSE voltage. This enables ratiometric measurements and integration with precision external references for calibration-critical applications.
What is the thermal pad connection requirement for the LTC2172IUKG-12#PBF QFN package?
The exposed thermal pad (Pin 53) of the LTC2172IUKG-12#PBF's 52-lead QFN package must be soldered directly to the PCB ground plane using multiple thermal vias. This connection is mandatory for both thermal dissipation (θJA = 28°C/W) and electrical stability, as the pad is internally connected to GND. Failure to solder the pad risks exceeding TJMAX = 150°C under full-load operation.
LTC2172IUKG-12#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 65M
- Number of Inputs:
- 4
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 4
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 52-QFN (7x8)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2172IUKG-12#PBF FAQ
1.How can I place an order for LTC2172IUKG-12#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2172IUKG-12#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2172IUKG-12#PBF reliable?
The price and inventory of LTC2172IUKG-12#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2172IUKG-12#PBF is usually 5 days.
3.What payment methods are accepted for LTC2172IUKG-12#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2172IUKG-12#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2172IUKG-12#PBF?
LTC2172IUKG-12#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2172IUKG-12#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2172IUKG-12#PBF?
For technical support, including LTC2172IUKG-12#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2172IUKG-12#PBF requirements.
6.How does Aetrix verify that LTC2172IUKG-12#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2172IUKG-12#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2172IUKG-12#PBF meets industry standards.
7.What is the process for return or replacement of LTC2172IUKG-12#PBF?
All LTC2172IUKG-12#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2172IUKG-12#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2172IUKG-12#PBF part is unused and in its original packaging.
Return procedure for LTC2172IUKG-12#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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