Analog Devices Inc. LTC2173CUKG-14#PBF
- Part No.:
- LTC2173CUKG-14#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 52-WFQFN Exposed Pad
- Datasheet:
-
LTC2173CUKG-14#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 52QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2173CUKG-14#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, 80Msps quad-channel simultaneous-sampling analog-to-digital converter optimized for wide dynamic range signal digitization in communications and instrumentation systems. It delivers 72.9dB SNR, 88dB SFDR, 0.15psRMS jitter, ±1LSB INL (typ), and operates from a single 1.8V supply with serial LVDS outputs - enabling high-fidelity undersampling of IF signals up to 140MHz in portable medical imaging and multichannel data acquisition.
For engineers reviewing the LTC2173CUKG-14#PBF datasheet, LTC2173CUKG-14#PBF pinout, LTC2173CUKG-14#PBF application, or LTC2173CUKG-14#PBF equivalent, this page provides verified specifications, validated pin functions, real-world use cases, and confirmed alternative parts - all aligned to the official LTC2173-14 datasheet Rev. D and Linear Technology product documentation.
Technical Context
The LTC2173CUKG-14#PBF implements four independent 14-bit ADC cores with shared sample-and-hold (800MHz full-power bandwidth) and integrated clock duty cycle stabilizer, supporting differential or single-ended encode inputs (PECL/LVDS/TTL/CMOS). Its architecture enables true simultaneous sampling across all channels without inter-channel skew.
Digital output serialization is configurable: 2-lane mode (two bits per channel per clock edge) at up to 80Msps, or 1-lane mode (one bit per channel) for reduced interface complexity. Internal 100Ω LVDS termination and adjustable output current (1.75mA/3.5mA) ensure robust signal integrity on controlled-impedance PCB traces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in precision measurement systems. |
| Sampling Rate | 80Msps maximum - supports Nyquist sampling of baseband signals up to 40MHz or undersampling of IF bands up to 140MHz. |
| SNR / SFDR | 72.9dB SNR and 88dB SFDR at 70MHz input - enables high-fidelity digitization of narrowband RF signals in SDR and base station receivers. |
| Jitter | 0.15psRMS aperture jitter - minimizes noise floor degradation when undersampling high-frequency analog inputs. |
| Power Consumption | 376mW total (94mW per channel) at 80Msps in 2-lane LVDS mode - enables thermally constrained portable and multi-channel embedded designs. |
| Analog Input Range | Selectable 1VP-P to 2VP-P differential range via SENSE pin - allows optimization for signal amplitude and noise performance without external gain stages. |
| Supply Voltage | Single 1.8V analog (VDD) and 1.8V output (OVDD) supplies - simplifies power delivery and reduces board-level DC/DC count. |
Pinout & Package
52-pin (7mm × 8mm) plastic QFN package with exposed thermal pad (Pin 53 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1+ / AIN1– AIN2+ / AIN2– AIN3+ / AIN3– AIN4+ / AIN4– |
Differential analog inputs (Ch.1–Ch.4) | Accepts 1–2VP-P differential signals; common-mode bias provided by VCM12/VCM34 pins - eliminates need for external common-mode generation circuitry. |
| VCM12 / VCM34 | Common-mode bias outputs | Nominally VDD/2 (0.9V); used to bias AIN pairs for Ch.1/2 and Ch.3/4 - ensures optimal ADC core operating point and linearity. |
| ENC+ / ENC– | Differential encode clock inputs | Supports differential (LVDS/PECL) or single-ended (TTL/CMOS) clocking; internal duty cycle stabilizer maintains timing accuracy across wide duty cycle variation. |
| OUT1A+/– to OUT4B+/– | LVDS serialized data outputs | Two differential pairs per channel (A/B) in 2-lane mode; programmable 1.75mA/3.5mA drive strength and optional 100Ω on-chip termination reduce layout sensitivity. |
| PAR/SER | Programming mode select | Ground = serial SPI control; VDD = parallel logic control (CS/SCK/SDI/SDO repurposed) - enables flexible configuration in resource-constrained systems. |
| SENSE | Reference and input range programming | Connect to VDD → ±1V range; to GND → ±0.5V range; to external 0.625–1.3V → ±0.8×VSENSE range - provides precise analog front-end scaling without external resistors. |
Key Features
| Feature | Design Value |
|---|---|
| Quad simultaneous sampling | Eliminates inter-channel timing skew - essential for phase-coherent beamforming, I/Q demodulation, and time-of-flight measurements. |
| Serial LVDS interface (1- or 2-lane) | Reduces digital I/O count by >60% vs parallel interfaces - lowers PCB layer count, EMI, and routing complexity in dense layouts. |
| Internal clock duty cycle stabilizer | Enables high-performance operation with non-50% duty cycle clocks - relaxes clock generator requirements in mixed-signal SoC environments. |
| Configurable input range & reference | Hardware-selectable 1VP-P/2VP-P differential input via SENSE pin - avoids calibration drift from external resistor dividers or op-amp gain stages. |
| Shutdown and Nap modes | 1mW Sleep and 85mW Nap power states - extends battery life in portable test equipment and intermittent-sampling sensor nodes. |
Applications
| Cellular Base Stations | Software Defined Radios |
|---|---|
|
Use Scenario: Digitizing multiple receive antenna paths in LTE/5G massive MIMO radio units. IC Role / Device Role / Timing Role: Simultaneous-sampling ADC capturing synchronized I/Q data streams from four RF front-ends. Use Value: 72.9dB SNR and 88dB SFDR preserve EVM and ACLR performance at 70–140MHz IF frequencies under real-world interference. |
Use Scenario: Reconfigurable wideband receiver in military comms or spectrum monitoring equipment. IC Role / Device Role / Timing Role: High-dynamic-range digitizer enabling real-time FFT analysis across 100MHz instantaneous bandwidth. Use Value: 0.15psRMS jitter and 800MHz S/H bandwidth support clean undersampling of 120MHz+ signals without external track-and-hold. |
| Portable Medical Imaging | Multichannel Data Acquisition |
|
Use Scenario: Ultrasound beamformer front-end acquiring echo return signals from phased-array transducers. IC Role / Device Role / Timing Role: Quad-channel ADC capturing time-aligned RF echoes with sub-nanosecond inter-channel skew. Use Value: Simultaneous sampling and ±1LSB INL ensure accurate time-of-flight calculation for spatial resolution down to 0.1mm. |
Use Scenario: High-precision vibration analysis system monitoring industrial machinery using four synchronized accelerometers. IC Role / Device Role / Timing Role: Low-power, low-noise ADC converting analog sensor outputs into time-coherent digital waveforms. Use Value: 376mW total power and 1.2LSBRMS transition noise enable battery-powered field deployment with >12-bit effective resolution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-channel, 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9257BCPZ-80 | 80Msps, 14-bit, quad-channel; 73.3dB SNR, 90dB SFDR; requires dual 1.8V/3.3V supplies; parallel CMOS outputs only. | Higher SFDR but lacks LVDS serialization and internal clock stabilizer - demands more PCB area and external clock conditioning. | Prefer AD9257BCPZ-80 when maximum spurious-free performance is critical and board space permits parallel bus routing. |
| LTC2174CUKG-14#PBF | 105Msps version of same family; identical pinout, package, and feature set; 73dB SNR, 88dB SFDR; 450mW total power. | Same architecture and software compatibility - direct upgrade path when higher sampling rate is required without layout change. | Choose LTC2174CUKG-14#PBF if system requires >80Msps sampling while retaining identical footprint and firmware. |
Compared with AD9257BCPZ-80 and LTC2174CUKG-14#PBF, the LTC2173CUKG-14#PBF offers the lowest power (376mW) and most flexible digital interface (programmable LVDS lanes + internal termination), making it optimal for portable, thermally constrained, or layout-sensitive designs where 80Msps suffices.
Availability
LTC2173CUKG-14#PBF is available at Aetrix Electronics and suitable for cellular base stations, portable medical imaging systems, and multichannel data acquisition requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC2173CUKG-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies.
The LTC2173CUKG-14#PBF belongs to the LTC217x-14 family of ultra-low-jitter quad ADCs designed specifically for demanding communications, instrumentation, and medical imaging applications requiring simultaneous sampling and wide dynamic range.
FAQ
What is the maximum sampling rate supported by the LTC2173CUKG-14#PBF?
The LTC2173CUKG-14#PBF supports a maximum sampling rate of 80Msps, as specified in the official datasheet. This rate is fixed for the LTC2173-14 speed grade and applies across all operating conditions and output modes. Higher rates (105Msps/125Msps) require the pin-compatible LTC2174-14 or LTC2175-14 variants, respectively.
Does the LTC2173CUKG-14#PBF support both serial and parallel configuration interfaces?
Yes, the LTC2173CUKG-14#PBF supports dual configuration modes via the PAR/SER pin. When grounded, it enables a 4-wire SPI interface (CS/SCK/SDI/SDO) for full register control. When tied to VDD, it switches to parallel logic mode where CS, SCK, SDI, and SDO become dedicated function pins for simplified hardware-based setup - no microcontroller firmware required.
What analog input voltage ranges does the LTC2173CUKG-14#PBF support, and how are they selected?
The LTC2173CUKG-14#PBF supports selectable differential input ranges of 1VP-P or 2VP-P, configured via the SENSE pin. Connecting SENSE to GND selects ±0.5V (1VP-P); to VDD selects ±1V (2VP-P); applying an external 0.625–1.3V reference selects ±0.8×VSENSE. No external components are needed - all scaling is handled internally.
How does the LTC2173CUKG-14#PBF achieve simultaneous sampling across all four channels?
The LTC2173CUKG-14#PBF uses a single, shared sample-and-hold (S/H) circuit with four independent 14-bit ADC cores - ensuring true simultaneous capture with zero inter-channel skew. This architecture is explicitly confirmed in the datasheet's "4-Channel Simultaneous Sampling ADC" feature list and timing diagrams, distinguishing it from multiplexed or staggered sampling approaches.
Is the LTC2173CUKG-14#PBF pin-compatible with other members of the LTC217x-14 family?
Yes, the LTC2173CUKG-14#PBF is fully pin-compatible with the LTC2174-14 and LTC2175-14 in the same 52-pin QFN package. All share identical pin functions, power requirements, and interface protocols - enabling drop-in upgrades to 105Msps or 125Msps without PCB redesign, provided thermal and layout margins accommodate higher power dissipation.
LTC2173CUKG-14#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 4
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 4
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 52-QFN (7x8)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2173CUKG-14#PBF FAQ
1.How can I place an order for LTC2173CUKG-14#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2173CUKG-14#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2173CUKG-14#PBF reliable?
The price and inventory of LTC2173CUKG-14#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2173CUKG-14#PBF is usually 5 days.
3.What payment methods are accepted for LTC2173CUKG-14#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2173CUKG-14#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2173CUKG-14#PBF?
LTC2173CUKG-14#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2173CUKG-14#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2173CUKG-14#PBF?
For technical support, including LTC2173CUKG-14#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2173CUKG-14#PBF requirements.
6.How does Aetrix verify that LTC2173CUKG-14#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2173CUKG-14#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2173CUKG-14#PBF meets industry standards.
7.What is the process for return or replacement of LTC2173CUKG-14#PBF?
All LTC2173CUKG-14#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2173CUKG-14#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2173CUKG-14#PBF part is unused and in its original packaging.
Return procedure for LTC2173CUKG-14#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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