Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Analog Devices Inc. LTC2174CUKG-12#PBF

Name: LTC2174CUKG-12#PBF
Brand: Analog Devices Inc.
SKU: LTC2174CUKG-12#PBF
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: LTC2174CUKG-12#PBF

Manufacturer:: Analog Devices Inc.

Category:: Analog to Digital Converters (ADC)

Package:: 52-WFQFN Exposed Pad

Datasheet:: LTC2174CUKG-12#PBF.pdf

Description:: IC ADC 12BIT PIPELINED 52QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,240

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

LTC2174CUKG-12#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 105 Msps quad-channel simultaneous-sampling analog-to-digital converter optimized for high-dynamic-range signal digitization in communications infrastructure. It delivers 70.6 dB SNR, 88 dB SFDR, and ultralow 0.15 ps_RMS aperture jitter, enabling undersampling of IF signals up to 140 MHz in cellular base stations and software-defined radios.

For engineers reviewing the LTC2174CUKG-12#PBF datasheet, LTC2174CUKG-12#PBF pinout, LTC2174CUKG-12#PBF application, or LTC2174CUKG-12#PBF equivalent, key selection criteria include its 4-channel synchronization capability, serial LVDS output architecture with 1-/2-lane mode flexibility, 1.8 V single-supply operation, and 52-pin QFN package with exposed thermal pad.

Technical Context

The LTC2174CUKG-12#PBF implements four independent 12-bit ADC cores with shared sample-and-hold circuitry and a common encode clock input, ensuring precise inter-channel timing alignment. Its internal duty cycle stabilizer maintains performance across wide clock duty cycle variations, and it supports both differential and single-ended clock drive (PECL/LVDS/TTL/CMOS).

Digital outputs use serial LVDS with configurable 1-bit-per-channel (1-lane) or 2-bit-per-channel (2-lane) serialization, selectable via CS/SCK pins. Internal 100 Ω LVDS termination and adjustable output current (1.75 mA / 3.5 mA) ensure robust signal integrity on high-speed PCB traces without external resistors.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	12-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in closed-loop control or precision measurement.
Sampling Rate	105 Msps - enables real-time digitization of wideband IF signals up to 800 MHz full-power bandwidth with minimal aliasing.
SNR @ 70 MHz	70.6 dBFS - provides >11.7 effective number of bits (ENOB) for high-fidelity signal capture in demanding RF receiver chains.
SFDR @ 70 MHz	88 dBFS - suppresses harmonics and spurs sufficiently for LTE/WiMAX base station channelization without additional filtering.
Aperture Jitter	0.15 ps_RMS - limits sampling uncertainty to <0.01 LSB at 140 MHz input, critical for undersampling architectures.
Power Dissipation	439 mW total (105 Msps, 2-lane, 1.75 mA mode) - balances performance and thermal management in dense multichannel systems.
Analog Supply	Single 1.8 V (1.7–1.9 V) - simplifies power delivery and reduces noise coupling versus dual-supply ADCs.

Pinout & Package

52-pin (7 mm × 8 mm) plastic QFN package with exposed thermal pad (Pin 53 = GND), rated for 0°C to 70°C operating temperature. Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.

Pin/Terminal	Circuit Role	Design Meaning
AIN1+ / AIN1– AIN2+ / AIN2– AIN3+ / AIN3– AIN4+ / AIN4–	Differential analog inputs (Ch. 1–4)	Accept 1–2 V_P-P differential signals; require matched trace lengths and 100 Ω termination for optimal AC performance.
VCM12 / VCM34	Common-mode bias outputs	Provide VDD/2 reference to bias input pairs; must be bypassed with 0.1 µF ceramic capacitors to GND.
ENC+ / ENC–	Differential encode clock inputs	Trigger simultaneous sampling on rising/falling edges; support DC-coupled sine, PECL, LVDS, TTL, or CMOS drive.
OUT1A+/– … OUT4B+/–	LVDS serialized data outputs	Deliver time-multiplexed 12-/14-/16-bit samples per channel; 2-lane mode outputs two bits per clock edge.
DCO+ / DCO– FR+ / FR–	Data clock and frame sync outputs	DCO aligns with serialized data edges; FR marks start of new 4-channel sample set - essential for deterministic FPGA capture.
PAR/SER CS SCK SDI SDO	Configuration interface	Enable serial SPI or parallel pin-strapped mode; SDO doubles as LVDS termination enable in parallel mode.

Key Features

Feature	Design Value
Quad-channel simultaneous sampling	Eliminates inter-channel skew in beamforming, MIMO, and phased-array receivers - no need for external synchronization logic.
Serial LVDS with 1-/2-lane mode	Reduces interface pin count by >60% vs parallel LVDS; 2-lane mode cuts FPGA I/O usage while maintaining 105 Msps throughput.
Internal clock duty cycle stabilizer	Enables use of low-cost crystal oscillators or FPGA-generated clocks with 20–80% duty cycle - avoids external duty cycle correction circuits.
Adjustable LVDS output current	1.75 mA or 3.5 mA per driver selectable via SCK - optimizes signal integrity for short or long PCB traces without redesign.
Shutdown and Nap modes	Reduces power to 1 mW (shutdown) or 85 mW (Nap) - preserves system-level power budget during idle periods in portable or battery-backed equipment.

Applications

Cellular Base Stations	Software Defined Radios
Use Scenario: Digitizing multiple 20–40 MHz LTE carrier bands in remote radio heads using direct IF sampling. IC Role / Device Role / Timing Role: Quad-channel ADC captures synchronized I/Q streams from quadrature demodulators; precise channel matching enables digital beam steering. Use Value: 88 dB SFDR prevents adjacent-channel interference; 0.15 ps jitter ensures EVM compliance below 2.5% at 256-QAM.	Use Scenario: Reconfigurable wideband receiver in military comms or spectrum monitoring systems covering 10 MHz–3 GHz. IC Role / Device Role / Timing Role: Simultaneous sampling across four channels supports real-time direction finding and interferometric processing. Use Value: 800 MHz full-power bandwidth allows first-Nyquist sampling of L/S-band signals; serial LVDS eases FPGA interface routing density.
Portable Medical Imaging	Multichannel Data Acquisition
Use Scenario: Ultrasound beamformer front-end digitizing echo returns from 64+ transducer elements in handheld scanners. IC Role / Device Role / Timing Role: Four LTC2174CUKG-12#PBF devices serve as channel groups, each handling 16 receive paths with matched gain/phase response. Use Value: ±0.3 LSB INL and ±0.1 LSB DNL preserve image contrast resolution; low 545 mW total power enables battery operation.	Use Scenario: High-precision vibration analysis in industrial predictive maintenance systems with 16+ sensor channels. IC Role / Device Role / Timing Role: Simultaneous sampling across multiple LTC2174CUKG-12#PBF units ensures phase-coherent FFT analysis of mechanical resonance modes. Use Value: 70.6 dB SNR resolves sub-milligal accelerations; SPI configuration allows runtime gain/range adjustment per channel group.

Cellular Base Stations

Software Defined Radios

Use Scenario: Digitizing multiple 20–40 MHz LTE carrier bands in remote radio heads using direct IF sampling.

IC Role / Device Role / Timing Role: Quad-channel ADC captures synchronized I/Q streams from quadrature demodulators; precise channel matching enables digital beam steering.

Use Value: 88 dB SFDR prevents adjacent-channel interference; 0.15 ps jitter ensures EVM compliance below 2.5% at 256-QAM.

Use Scenario: Reconfigurable wideband receiver in military comms or spectrum monitoring systems covering 10 MHz–3 GHz.

IC Role / Device Role / Timing Role: Simultaneous sampling across four channels supports real-time direction finding and interferometric processing.

Use Value: 800 MHz full-power bandwidth allows first-Nyquist sampling of L/S-band signals; serial LVDS eases FPGA interface routing density.

Portable Medical Imaging

Multichannel Data Acquisition

Use Scenario: Ultrasound beamformer front-end digitizing echo returns from 64+ transducer elements in handheld scanners.

IC Role / Device Role / Timing Role: Four LTC2174CUKG-12#PBF devices serve as channel groups, each handling 16 receive paths with matched gain/phase response.

Use Value: ±0.3 LSB INL and ±0.1 LSB DNL preserve image contrast resolution; low 545 mW total power enables battery operation.

Use Scenario: High-precision vibration analysis in industrial predictive maintenance systems with 16+ sensor channels.

IC Role / Device Role / Timing Role: Simultaneous sampling across multiple LTC2174CUKG-12#PBF units ensures phase-coherent FFT analysis of mechanical resonance modes.

Use Value: 70.6 dB SNR resolves sub-milligal accelerations; SPI configuration allows runtime gain/range adjustment per channel group.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-channel, 12-bit ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD9255BCPZ-105	14-bit, 105 Msps; JESD204B serial interface; higher 73.5 dB SNR but 750 mW power	Requires FPGA with JESD204B IP; better for high-ENOB applications where power is secondary	Select when >12-bit resolution and deterministic lane alignment are required; not pin-compatible.
LTC2173CUKG-12#PBF	Same family, 80 Msps speed grade; identical pinout, register map, and features at lower power (369 mW)	Suitable for cost-sensitive or thermally constrained designs where 80 Msps suffices (e.g., narrowband IoT gateways)	Drop-in replacement if sampling rate reduction is acceptable; shares same PCB layout and firmware.

Compared with AD9255BCPZ-105, the LTC2174CUKG-12#PBF offers lower power and simpler LVDS interface but trades 2 bits of resolution; compared with LTC2173CUKG-12#PBF, it delivers 25% higher throughput with identical footprint and software compatibility - ideal for upgrade paths in existing designs.

Availability

LTC2174CUKG-12#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio development, and portable medical imaging requiring stable component supply and long-term production continuity.

Supply support for LTC2174CUKG-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its high-performance signal chain portfolio, emphasizing precision, speed, and integration for demanding analog applications.

The LTC217x family targets high-speed, multichannel digitization in communications, instrumentation, and medical systems - designed specifically for simultaneous sampling, low jitter, and flexible digital interfacing without sacrificing dynamic range.

FAQ

What is the maximum input frequency supported by the LTC2174CUKG-12#PBF?

The LTC2174CUKG-12#PBF features an 800 MHz full-power bandwidth sample-and-hold amplifier, enabling accurate digitization of analog inputs up to 800 MHz. For undersampling applications, it reliably captures signals at 70 MHz, 140 MHz, and beyond with 70.6 dB SNR and 88 dB SFDR - verified in typical performance plots across input frequencies.

Does the LTC2174CUKG-12#PBF support both differential and single-ended clock inputs?

Yes, the LTC2174CUKG-12#PBF supports both configurations: ENC+ and ENC– accept differential inputs (LVDS, PECL, sine wave), while ENC– can be tied to GND to enable single-ended mode driven by TTL, CMOS, or 1.8 V square waves. The internal duty cycle stabilizer ensures consistent performance regardless of input type.

How many bits per channel does the LTC2174CUKG-12#PBF output in 2-lane LVDS mode?

In 2-lane LVDS mode, the LTC2174CUKG-12#PBF outputs two serialized bits per channel per clock cycle - delivering 12-, 14-, or 16-bit words depending on configuration. Each channel's data is multiplexed across OUTxA+/– and OUTxB+/– pairs, with DCO and FR signals providing timing alignment for FPGA capture.

What is the purpose of the PAR/SER pin on the LTC2174CUKG-12#PBF?

The PAR/SER pin on the LTC2174CUKG-12#PBF selects the programming interface mode: grounded for serial SPI (using CS/SCK/SDI/SDO), or tied to VDD for parallel pin-strapped configuration. In parallel mode, CS and SCK repurpose to select 1-/2-lane output and 1.75-/3.5-mA LVDS drive strength - eliminating need for SPI transactions during initialization.

Can the LTC2174CUKG-12#PBF operate from a single 1.8 V supply?

Yes, the LTC2174CUKG-12#PBF operates from a single 1.8 V analog supply (VDD = 1.7–1.9 V) and a separate 1.8 V output driver supply (OVDD = 1.7–1.9 V). This dual-rail 1.8 V architecture isolates analog and digital switching noise, preserving 70.6 dB SNR without requiring additional voltage regulators or level shifters.

LTC2174CUKG-12#PBF Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 52-WFQFN Exposed Pad

Packaging:: Tube

Product Status:: Active

Number of Bits:: 12

Sampling Rate (Per Second):: 105M

Number of Inputs:: 4

Input Type:: Differential

Data Interface:: LVDS - Serial

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 4

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 1.7V ~ 1.9V

Voltage - Supply, Digital:: 1.7V ~ 1.9V

Features:: Simultaneous Sampling

Operating Temperature:: 0°C ~ 70°C

Supplier Device Package:: 52-QFN (7x8)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

LTC2174CUKG-12#PBF FAQ

1.How can I place an order for LTC2174CUKG-12#PBF through Aetrix?

Please submit a Request for Quotation (RFQ) for LTC2174CUKG-12#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LTC2174CUKG-12#PBF reliable?

The price and inventory of LTC2174CUKG-12#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2174CUKG-12#PBF is usually 5 days.

3.What payment methods are accepted for LTC2174CUKG-12#PBF?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2174CUKG-12#PBF transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for LTC2174CUKG-12#PBF?

LTC2174CUKG-12#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LTC2174CUKG-12#PBF order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LTC2174CUKG-12#PBF?

For technical support, including LTC2174CUKG-12#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2174CUKG-12#PBF requirements.

6.How does Aetrix verify that LTC2174CUKG-12#PBF is sourced from the original manufacturer or authorized distributors?

All LTC2174CUKG-12#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2174CUKG-12#PBF meets industry standards.

7.What is the process for return or replacement of LTC2174CUKG-12#PBF?

All LTC2174CUKG-12#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2174CUKG-12#PBF, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LTC2174CUKG-12#PBF part is unused and in its original packaging.

Return procedure for LTC2174CUKG-12#PBF:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…