Analog Devices Inc. LTC2174CUKG-14#PBF
- Part No.:
- LTC2174CUKG-14#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 52-WFQFN Exposed Pad
- Datasheet:
-
LTC2174CUKG-14#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 52QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2174CUKG-14#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, 105 Msps quad-channel simultaneous-sampling analog-to-digital converter optimized for high-dynamic-range signal digitization in communications infrastructure. It delivers 72.6 dB SNR at 70 MHz input, 88 dB SFDR, and ultralow 0.15 psRMS aperture jitter, enabling undersampling of IF signals in cellular base stations and software-defined radios.
For engineers reviewing the LTC2174CUKG-14#PBF datasheet, LTC2174CUKG-14#PBF pinout, LTC2174CUKG-14#PBF application, or LTC2174CUKG-14#PBF equivalent, this page provides verified package mapping (52-pin 7mm × 8mm QFN), confirmed LVDS serialization modes (1-/2-lane), validated input range selection (1–2 VP-P), and real-world performance data across temperature and frequency.
Technical Context
The LTC2174CUKG-14#PBF implements four independent 14-bit ADC cores with shared sample-and-hold and internal clock duty cycle stabilizer, supporting differential or single-ended encode inputs (PECL/LVDS/TTL/CMOS). Its 800 MHz full-power bandwidth enables wideband RF sampling up to 140 MHz.
Digital outputs use serial LVDS with programmable 1.75 mA or 3.5 mA drive strength and optional on-chip 100 Ω termination. Configuration is handled via SPI port or parallel logic pins (PAR/SER mode), with dedicated shutdown and nap modes reducing power to 85 mW and 1 mW respectively.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in precision measurement systems. |
| Sampling Rate | 105 Msps - supports Nyquist sampling of signals up to 52.5 MHz or undersampling of IF bands up to 140 MHz. |
| SNR @ 70 MHz | 72.6 dBFS - enables >12-bit effective resolution for demanding receiver applications like LTE eNodeB front-ends. |
| SFDR @ 70 MHz | 88 dBFS - suppresses harmonics and spurs critical for multi-carrier cellular and radar signal integrity. |
| Aperture Jitter | 0.15 psRMS - limits sampling uncertainty to <0.01 LSB at 140 MHz input, essential for high-IF digitization. |
| Power Dissipation | 450 mW total (113 mW/channel) at 105 Msps, 2-lane LVDS - balances performance and thermal management in dense PCB layouts. |
| Analog Supply | Single 1.8 V (VDD), ±5% tolerance - simplifies power delivery and reduces noise coupling versus dual-supply ADCs. |
Pinout & Package
52-pin plastic QFN package (7 mm × 8 mm), exposed pad soldered to PCB ground per datasheet requirement. Pin count and layout match LTC2175-14 and LTC2173-14 for family-level board compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1+ / AIN1– | Channel 1 differential analog input | Accepts 1–2 VP-P differential signal; common-mode bias provided by VCM12. |
| VCM12 | Common-mode bias output (Ch1/Ch2) | Nominally VDD/2; must be bypassed with 0.1 µF capacitor to ground for stable input biasing. |
| ENC+ / ENC– | Differential encode clock input | Triggers conversion on both edges; supports duty cycle stabilization for jitter-sensitive clocks. |
| OUT1A+/OUT1A– | LVDS serial data output (Ch1, Lane A) | Transmits 2 bits per cycle in 2-lane mode; configurable for 1.75 mA or 3.5 mA current drive. |
| FR+/FR– | Frame clock output | Indicates start of new sample frame; period equals two encode cycles in 2-lane mode. |
| PAR/SER | Programming mode select | Ground = serial SPI control; VDD = parallel logic control (CS/SCK/SDI/SDO repurposed). |
| SENSE | Reference programming input | Configures input range: VDD = ±1 V, GND = ±0.5 V, external 0.625–1.3 V = ±0.8×VSENSE. |
| Exposed Pad (Pin 53) | Thermal and electrical ground | Must be soldered to PCB ground plane with multiple vias for thermal dissipation and noise reduction. |
Key Features
| Feature | Design Value |
|---|---|
| Quad simultaneous sampling | Enables coherent multichannel acquisition for beamforming, MIMO, and phase-sensitive instrumentation without inter-channel skew. |
| Serial LVDS interface (1-/2-lane) | Reduces interface pin count by >50% vs parallel CMOS; supports trace-length matching and EMI resilience in high-speed PCB routing. |
| Programmable input range (1–2 VP-P) | Allows optimization of dynamic range against system noise floor and driver capability without external gain stages. |
| Internal clock duty cycle stabilizer | Permits use of asymmetric clocks (e.g., from PLLs or crystal oscillators) while maintaining full AC performance at 105 Msps. |
| Shutdown and nap modes | Reduces power to 1 mW (shutdown) or 85 mW (nap) during idle periods-critical for battery-backed or thermally constrained SDR platforms. |
Applications
| Cellular Base Stations | Software Defined Radios |
|---|---|
|
Use Scenario: Digitizing 20–40 MHz wide LTE/5G NR uplink/downlink IF signals centered at 70–140 MHz in macrocell remote radio heads. IC Role / Device Role / Timing Role: Quad-channel ADC providing synchronized I/Q sampling for digital predistortion and MIMO channel estimation. Use Value: 88 dB SFDR prevents adjacent-channel interference; 0.15 psRMS jitter maintains EVM <1% at 256-QAM. |
Use Scenario: Reconfigurable RF front-end in portable military/commercial SDRs requiring multi-band operation from HF to 2 GHz. IC Role / Device Role / Timing Role: High-fidelity digitizer enabling real-time spectrum analysis and adaptive waveform processing across bands. Use Value: 72.6 dB SNR ensures >70 dB spurious-free resolution; 105 Msps sampling supports instantaneous bandwidth up to 52.5 MHz. |
| Portable Medical Imaging | Multichannel Data Acquisition |
|
Use Scenario: Ultrasound beamformer digitizing 10–15 MHz echo returns from 64+ transducer elements in handheld scanners. IC Role / Device Role / Timing Role: Simultaneous-sampling ADC capturing time-aligned RF echoes for synthetic aperture focusing. Use Value: 14-bit resolution and ±1 LSB INL preserve tissue contrast; low power enables battery operation without active cooling. |
Use Scenario: High-precision vibration monitoring in industrial predictive maintenance systems using 4-channel synchronized sensor inputs. IC Role / Device Role / Timing Role: Time-coherent digitizer for FFT-based spectral analysis of mechanical resonance signatures. Use Value: 800 MHz input bandwidth captures harmonics up to 10th order; 73 dB SNR resolves sub-millig acceleration changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-channel, 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9694BCPZ-1000 | 14-bit, 1 GSPS quad ADC with JESD204B interface; higher speed but 2.5× power (1.2 W); requires FPGA with JESD support. | Targets 5G massive MIMO and radar where >500 MSPS sustained throughput is required. | Select when system demands >500 MSPS aggregate sampling or JESD204B backhaul; avoid if LVDS simplicity and 450 mW power budget are critical. |
| LTC2173CUKG-14#PBF | Same pinout and architecture, but 80 Msps max; 376 mW power; identical SNR/SFDR specs scaled to lower rate. | Suitable for cost-optimized or lower-bandwidth applications (e.g., narrowband IoT gateways, legacy 3G infrastructure). | Select for BOM rationalization within LTC217x family when 80 Msps suffices; retains full software/hardware compatibility with no layout change. |
Compared with AD9694BCPZ-1000, the LTC2174CUKG-14#PBF offers LVDS simplicity and 62% lower power at the expense of raw speed; compared with LTC2173CUKG-14#PBF, it delivers 31% higher sampling rate with only 20% more power, making it optimal for mid-tier 4G/5G infrastructure where 105 Msps is the design sweet spot.
Availability
LTC2174CUKG-14#PBF is available at Aetrix Electronics and suitable for cellular base station development, software-defined radio prototyping, and portable medical imaging systems requiring stable component supply and long-term industrial availability.
Supply support for LTC2174CUKG-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and DSP solutions for precision instrumentation, communications, and industrial markets.
The LTC2174CUKG-14#PBF belongs to the LTC217x family of ultra-low-jitter quad ADCs designed specifically for high-dynamic-range digitization in wireless infrastructure and test equipment where SNR, SFDR, and timing fidelity are non-negotiable.
FAQ
What is the maximum sampling rate supported by the LTC2174CUKG-14#PBF?
The LTC2174CUKG-14#PBF supports a maximum sampling rate of 105 Msps, as specified in its speed grade designation and confirmed in the Absolute Maximum Ratings table. This rate is achievable with 2-lane LVDS serialization and 1.8 V supplies; exceeding 105 Msps risks violating timing margins and degrading SNR/SFDR performance. The LTC2174CUKG-14#PBF is distinct from the faster LTC2175-14 (125 Msps) and slower LTC2173-14 (80 Msps) variants in the same family.
Does the LTC2174CUKG-14#PBF support external reference configuration?
Yes, the LTC2174CUKG-14#PBF supports external reference configuration via the SENSE pin. Applying a voltage between 0.625 V and 1.3 V to SENSE sets the input range to ±0.8 × VSENSE, allowing precise scaling for custom signal chains. The device also supports internal reference modes (±0.5 V or ±1 V) by tying SENSE to GND or VDD, respectively. All configurations maintain the same 14-bit resolution and linearity specs of the LTC2174CUKG-14#PBF.
What LVDS serialization modes does the LTC2174CUKG-14#PBF offer?
The LTC2174CUKG-14#PBF offers two LVDS serialization modes: 2-lane (two bits per channel per clock cycle) and 1-lane (one bit per channel per clock cycle). Mode selection is controlled by the CS pin in parallel programming mode (PAR/SER = VDD). In 2-lane mode, the LTC2174CUKG-14#PBF outputs OUTxA+/OUTxA– and OUTxB+/OUTxB– per channel; in 1-lane mode, only OUTxA+/OUTxA– are active and OUTxB pins are disabled.
How is the common-mode voltage managed for the analog inputs of the LTC2174CUKG-14#PBF?
The LTC2174CUKG-14#PBF provides two dedicated common-mode bias outputs: VCM12 for channels 1 and 2, and VCM34 for channels 3 and 4. Each outputs nominally VDD/2 (0.9 V at 1.8 V supply) and must be bypassed to ground with a 0.1 µF ceramic capacitor. These outputs directly bias the differential analog inputs (e.g., AIN1+/AIN1–), eliminating the need for external resistive dividers and ensuring matched common-mode levels across all four channels of the LTC2174CUKG-14#PBF.
What power-saving features are available on the LTC2174CUKG-14#PBF?
The LTC2174CUKG-14#PBF includes two hardware-controlled power-saving states: Nap mode (85 mW total power) and Shutdown mode (1 mW). Nap mode preserves register settings and allows fast wake-up (<1 µs), while Shutdown mode powers down all circuitry except the bandgap reference. Both modes are activated via the SDI pin in parallel programming mode, enabling dynamic power management in battery-powered or thermally constrained applications using the LTC2174CUKG-14#PBF.
LTC2174CUKG-14#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 105M
- Number of Inputs:
- 4
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 4
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 52-QFN (7x8)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2174CUKG-14#PBF FAQ
1.How can I place an order for LTC2174CUKG-14#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2174CUKG-14#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2174CUKG-14#PBF reliable?
The price and inventory of LTC2174CUKG-14#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2174CUKG-14#PBF is usually 5 days.
3.What payment methods are accepted for LTC2174CUKG-14#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2174CUKG-14#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2174CUKG-14#PBF?
LTC2174CUKG-14#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2174CUKG-14#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2174CUKG-14#PBF?
For technical support, including LTC2174CUKG-14#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2174CUKG-14#PBF requirements.
6.How does Aetrix verify that LTC2174CUKG-14#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2174CUKG-14#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2174CUKG-14#PBF meets industry standards.
7.What is the process for return or replacement of LTC2174CUKG-14#PBF?
All LTC2174CUKG-14#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2174CUKG-14#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2174CUKG-14#PBF part is unused and in its original packaging.
Return procedure for LTC2174CUKG-14#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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