Analog Devices Inc. LTC2174IUKG-12#PBF
- Part No.:
- LTC2174IUKG-12#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 52-WFQFN Exposed Pad
- Datasheet:
-
LTC2174IUKG-12#PBF.pdf
- Description:
- IC ADC 12BIT PIPELINED 52QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,240
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2174IUKG-12#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 105 Msps quad-channel simultaneous-sampling analog-to-digital converter optimized for high-dynamic-range RF/IF digitization. It delivers 70.6 dB SNR, 88 dB SFDR, and ultralow 0.15 psRMS aperture jitter at full speed, enabling undersampling of 70–140 MHz IF signals in cellular base stations and software-defined radios.
For engineers reviewing the LTC2174IUKG-12#PBF datasheet, LTC2174IUKG-12#PBF pinout, LTC2174IUKG-12#PBF application, or LTC2174IUKG-12#PBF equivalent, key selection criteria include guaranteed ±0.3 LSB INL over –40°C to +85°C, serial LVDS 1-/2-lane output flexibility, 1.8 V single-supply operation, and 800 MHz full-power bandwidth with differential input support.
Technical Context
The LTC2174IUKG-12#PBF implements four independent 12-bit ADC cores with shared clocking and synchronization logic, enabling true simultaneous sampling across all channels. Its internal duty cycle stabilizer maintains performance across wide input clock duty cycles (2%–98%), and its sample-and-hold supports full-power bandwidth up to 800 MHz.
Digital interface uses serial LVDS outputs with programmable 1-bit-per-channel (1-lane) or 2-bit-per-channel (2-lane) serialization, selectable via CS/SCK pins. Internal reference provides 1.25 V ±25 ppm/°C drift, while external reference mode accepts 0.625–1.300 V on SENSE pin with ±0.2% gain matching between channels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes over temperature - ensures monotonicity and deterministic code transitions in closed-loop control or spectral analysis. |
| Sampling Rate | 105 Msps maximum - supports Nyquist sampling of signals up to 52.5 MHz or undersampling of IF bands up to 140 MHz with alias rejection. |
| SNR / SFDR | 70.6 dB SNR and 88 dB SFDR at 70 MHz input - enables high-fidelity digitization of multi-tone LTE/WCDMA signals without spurious corruption. |
| Aperture Jitter | 0.15 psRMS - limits sampling uncertainty to <0.01° phase error at 140 MHz, critical for coherent MIMO receiver calibration. |
| Power Consumption | 439 mW total at 105 Msps (2-lane, 1.75 mA LVDS) - enables thermal management in dense multichannel data acquisition systems. |
| Analog Input Range | Selectable 1 VP-P to 2 VP-P differential - simplifies front-end gain staging for variable signal amplitudes in portable medical imaging. |
| Operating Temperature | –40°C to +85°C industrial grade - qualified for deployment in outdoor base station cabinets and industrial test equipment. |
Pinout & Package
52-pin (7 mm × 8 mm) plastic QFN package with exposed thermal pad (Pin 53 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1+ / AIN1– (Pins 1,2) | Channel 1 differential analog input | Accepts 1–2 VP-P differential signal; common-mode bias provided by VCM12 (Pin 3). |
| VCM12 (Pin 3) | Common-mode bias for Ch1/Ch2 | Nominally VDD/2 (0.9 V); must be bypassed with 0.1 µF capacitor to GND for noise immunity. |
| ENC+ / ENC– (Pins 17,18) | Differential encode clock input | Supports PECL/LVDS/TTL/CMOS; rising/falling edge triggers conversion; internal duty cycle stabilizer enabled. |
| OUT1A+/OUT1A– (Pins 35,36) | LVDS data output lane A, Channel 1 | 2-lane mode: carries bits D1/D0; 1-lane mode: disabled; internal 100 Ω termination optional via SDO pin. |
| FR+/FR– (Pins 39,40) | Frame clock output | Indicates start of new sample frame; period equals 2× ENC period in 2-lane mode. |
| PAR/SER (Pin 47) | Programming mode select | Ground = serial SPI mode; VDD = parallel pin-strapped mode for configuration without firmware overhead. |
Key Features
| Feature | Design Value |
|---|---|
| Quad simultaneous sampling | Eliminates inter-channel skew (<1 ps), enabling precise phase-coherent beamforming in phased-array radar receivers. |
| Serial LVDS with 1-/2-lane mode | Reduces interface routing density by 50% vs parallel LVDS; supports FPGA I/O with limited SERDES lanes. |
| Internal clock duty cycle stabilizer | Allows use of low-cost crystal oscillators or asymmetric clocks without SNR degradation at full 105 Msps rate. |
| Shutdown and Nap modes | Reduces power to 1 mW (shutdown) or 85 mW (Nap) - extends battery life in portable spectrum analyzers and handheld test gear. |
| Pin-compatible family | Shares footprint and pinout with LTC2175-12 (125 Msps) and LTC2173-12 (80 Msps), enabling scalable platform design. |
Applications
| Cellular Base Stations | Software Defined Radios |
|---|---|
|
Use Scenario: Digitizing dual-polarized MIMO RF paths in LTE-Advanced macrocells with real-time channel estimation. IC Role / Device Role / Timing Role: Simultaneous sampling ADC capturing synchronized I/Q pairs per antenna branch at 105 Msps. Use Value: 88 dB SFDR prevents adjacent-channel interference masking weak user signals; 0.15 ps jitter preserves EVM under 256-QAM modulation. |
Use Scenario: Reconfigurable wideband receiver front-end supporting multiple waveforms (FM, DMR, TETRA, LTE) in military comms. IC Role / Device Role / Timing Role: High-dynamic-range digitizer feeding FPGA-based digital downconverters and demodulators. Use Value: 70.6 dB SNR enables >120 dB dynamic range after digital filtering; 1.8 V supply simplifies power architecture alongside Xilinx Zynq SoCs. |
| Portable Medical Imaging | Multichannel Data Acquisition |
|
Use Scenario: Ultrasound beamformer with 64-channel receive path requiring time-aligned echo sampling. IC Role / Device Role / Timing Role: Quad-channel ADC per module, cascaded across 16 modules for full-system 64-channel capture. Use Value: ±0.3 LSB INL ensures accurate B-mode image contrast; 800 MHz bandwidth supports harmonic imaging up to 15 MHz transducer frequencies. |
Use Scenario: High-precision vibration monitoring system with 16 sensor inputs across rotating machinery. IC Role / Device Role / Timing Role: Four synchronized 12-bit converters per LTC2174IUKG-12#PBF, deployed across four PCBs for distributed sensing. Use Value: –105 dBc far-channel crosstalk prevents coupling between adjacent accelerometer channels; 439 mW power enables fanless enclosure design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-channel, 12-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9257BSTZ-105 | 14-bit resolution, 105 Msps, JESD204B output; higher power (720 mW), no internal reference | Better ENOB for precision instrumentation; requires external serializer and clock distribution IC | Choose AD9257BSTZ-105 when 14-bit resolution and JESD204B backplane integration outweigh added complexity and power cost. |
| LTC2173IUKG-12#PBF | Same pinout, 80 Msps max, lower power (369 mW), identical AC specs at reduced rate | Lower sampling headroom but sufficient for narrowband IF digitization in cost-sensitive test equipment | Choose LTC2173IUKG-12#PBF when 80 Msps meets system bandwidth needs and thermal budget is tighter than 439 mW. |
Compared with LTC2174IUKG-12#PBF, AD9257BSTZ-105 trades simplicity and integrated reference for higher resolution and serial interface scalability, while LTC2173IUKG-12#PBF offers identical form factor and reliability at reduced speed and power-enabling drop-in rate scaling without layout change.
Availability
LTC2174IUKG-12#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, defense communications, portable medical imaging, and industrial multichannel data acquisition requiring stable component supply across extended temperature ranges.
Supply support for LTC2174IUKG-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and continues its legacy of high-performance signal chain components for demanding analog-intensive applications.
The LTC2174IUKG-12#PBF belongs to the LTC217x family of quad, simultaneous-sampling ADCs designed specifically for wideband communications and instrumentation where channel coherence, low jitter, and low power are non-negotiable.
FAQ
What is the maximum sampling rate supported by the LTC2174IUKG-12#PBF?
The LTC2174IUKG-12#PBF supports a maximum sampling rate of 105 Msps. This is its designated speed grade within the LTC217x family-distinct from the 125 Msps LTC2175-12 and 80 Msps LTC2173-12. Operation above 105 Msps is not characterized or guaranteed, and timing violations may occur in LVDS serialization or pipeline latency.
Does the LTC2174IUKG-12#PBF require an external reference voltage?
No, the LTC2174IUKG-12#PBF includes a precision internal reference (1.250 V ±25 ppm/°C) that can be used directly. However, it also supports external reference mode via the SENSE pin (0.625–1.300 V), which improves gain matching to ±0.2%FS across all four channels-critical for multichannel amplitude calibration.
How does the serial LVDS interface of the LTC2174IUKG-12#PBF operate in 1-lane vs 2-lane mode?
In 2-lane mode, each channel outputs two bits per sample (e.g., D1/D0) on dedicated LVDS pairs (OUTxA+/–, OUTxB+/–), doubling data throughput. In 1-lane mode, only OUTxA+/– is active per channel, carrying one bit per sample-halving interface pin count and power (IOVDD drops ~20 mA) at the cost of doubled serialization clock frequency.
What is the operating temperature range of the LTC2174IUKG-12#PBF?
The LTC2174IUKG-12#PBF is rated for industrial operation from –40°C to +85°C. This is confirmed by its "I" grade suffix and the Absolute Maximum Ratings table, which specifies the same range for all LTC2174I variants. Performance parameters like INL (±0.3 LSB), SNR (70.6 dB), and SFDR (88 dB) are guaranteed across this full range.
Can the LTC2174IUKG-12#PBF be used with single-ended clock inputs?
Yes-the ENC– pin can be tied to GND to enable single-ended encode mode. In this configuration, ENC+ accepts TTL, CMOS, or LVDS logic levels (0.6–3.6 V), with VIH ≥1.2 V and VIL ≤0.6 V at VDD = 1.8 V. The internal duty cycle stabilizer remains active, preserving timing performance even with asymmetric input waveforms.
LTC2174IUKG-12#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 105M
- Number of Inputs:
- 4
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 4
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 52-QFN (7x8)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2174IUKG-12#PBF FAQ
1.How can I place an order for LTC2174IUKG-12#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2174IUKG-12#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2174IUKG-12#PBF reliable?
The price and inventory of LTC2174IUKG-12#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2174IUKG-12#PBF is usually 5 days.
3.What payment methods are accepted for LTC2174IUKG-12#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2174IUKG-12#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2174IUKG-12#PBF?
LTC2174IUKG-12#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2174IUKG-12#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2174IUKG-12#PBF?
For technical support, including LTC2174IUKG-12#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2174IUKG-12#PBF requirements.
6.How does Aetrix verify that LTC2174IUKG-12#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2174IUKG-12#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2174IUKG-12#PBF meets industry standards.
7.What is the process for return or replacement of LTC2174IUKG-12#PBF?
All LTC2174IUKG-12#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2174IUKG-12#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2174IUKG-12#PBF part is unused and in its original packaging.
Return procedure for LTC2174IUKG-12#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2174IUKG-12#PBF Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

