Analog Devices Inc. LTC2175CUKG-14#PBF
- Part No.:
- LTC2175CUKG-14#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 52-WFQFN Exposed Pad
- Datasheet:
-
LTC2175CUKG-14#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 52QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,114
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2175CUKG-14#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, 125Msps quad simultaneous-sampling analog-to-digital converter optimized for high-dynamic-range RF/IF digitization. It delivers 73.1dB SNR, 88dB SFDR, and ultralow 0.15psRMS jitter at full speed, enabling undersampling of 70–140MHz IF signals in cellular base stations and software-defined radios.
For engineers reviewing the LTC2175CUKG-14#PBF datasheet, LTC2175CUKG-14#PBF pinout, LTC2175CUKG-14#PBF application, or LTC2175CUKG-14#PBF equivalent, this page provides verified package mapping (52-pin QFN), confirmed LVDS serialization modes (1-/2-lane), validated input range selection (1–2VP-P), and real-world performance data including crosstalk (–90dBc near-channel), pipeline latency (6 cycles), and power consumption (558mW total at 125Msps).
Technical Context
The LTC2175CUKG-14#PBF integrates four independent 14-bit ADC cores with shared sample-and-hold (800MHz full-power bandwidth) and a duty-cycle-stabilized differential encode interface. Its serial LVDS outputs support programmable 1.75mA/3.5mA drive strength and internal 100Ω termination, reducing PCB routing complexity versus parallel-output ADCs.
It features dual reference options (internal 1.25V ±25ppm/°C or external 0.625–1.3V), SPI-configurable serialization (12-/14-/16-bit per lane), and low-power states (85mW Nap, 1mW Sleep). Channel matching is specified at ±0.2%FS gain and ±3mV offset over temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in precision measurement systems. |
| Sampling Rate | 125Msps maximum - supports Nyquist sampling of up to 62.5MHz baseband or undersampling of 70–140MHz IF bands. |
| SNR / SFDR | 73.1dB SNR and 88dB SFDR at 70MHz input - enables high-fidelity signal capture in demanding comms receivers. |
| Input Bandwidth | 800MHz full-power bandwidth - preserves signal integrity for wideband RF inputs without external filtering penalties. |
| Power Consumption | 558mW total at 125Msps (140mW/channel) - achieves high-speed performance with single 1.8V supply, simplifying power delivery. |
| Jitter | 0.15psRMS aperture jitter - minimizes noise floor degradation when undersampling high-frequency signals. |
| Supply Voltage | 1.8V analog (VDD) and 1.8V output (OVDD) - eliminates need for multiple supply rails and reduces board-level complexity. |
Pinout & Package
Package: 52-lead (7mm × 8mm) plastic QFN with exposed pad (Pin 53 = GND), rated for 0°C to 70°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1+ / AIN1– (Pins 1, 2) | Channel 1 differential analog input | Accepts 1–2VP-P differential signal; common-mode bias provided by VCM12 (Pin 3). |
| ENC+ / ENC– (Pins 17, 18) | Differential encode clock input | Triggers conversion on both edges; supports sine wave, PECL, LVDS, TTL, or CMOS drive with internal duty-cycle stabilization. |
| OUT1A+/OUT1A– (Pins 41, 42) | LVDS data output lane A, Channel 1 | Serial 2-bit output in 2-lane mode; configurable for 1-/2-lane operation via CS/SCK in parallel programming mode. |
| FR+/FR– (Pins 27, 28) | LVDS frame clock output | Indicates start of new sample frame; period equals two encode cycles in 2-lane mode. |
| PAR/SER (Pin 47) | Programming mode select | Ground = serial SPI interface (CS/SCK/SDI/SDO); VDD = parallel logic control (CS/SCK/SDI/SDO as GPIO). |
| SENSE (Pin 50) | Reference and input range programming | Determines input range: VDD = ±1V, GND = ±0.5V, external 0.625–1.3V = ±0.8×VSENSE. |
Key Features
| Feature | Design Value |
|---|---|
| Quad simultaneous sampling | Enables coherent multichannel acquisition for beamforming, MIMO, or phase-sensitive instrumentation without inter-channel skew. |
| Serial LVDS interface (1-/2-lane) | Reduces digital I/O count from 56 (parallel) to 8–16 pins, easing high-speed layout and lowering EMI in dense RF assemblies. |
| Programmable LVDS output current | 1.75mA or 3.5mA per differential pair - allows optimization of signal integrity vs. power across varying trace lengths and loads. |
| Internal clock duty-cycle stabilizer | Maintains <±10% duty cycle tolerance - ensures consistent sampling aperture timing even with asymmetric clock sources. |
| Configurable power modes | Nap (85mW) and Sleep (1mW) states enable rapid wake-up for burst-mode operation in battery-powered SDR or portable test equipment. |
| On-chip 100Ω LVDS termination | Eliminates need for external termination resistors - saves board space and improves impedance matching consistency across channels. |
Applications
| Cellular Base Stations | Software Defined Radios |
|---|---|
|
Use Scenario: Digitizing multiple 20–40MHz LTE/5G NR carrier bands simultaneously in remote radio units. IC Role / Device Role / Timing Role: Quad-channel IF sampling ADC with synchronized capture across all four receivers for channel bonding and interference cancellation. Use Value: 88dB SFDR prevents adjacent-channel leakage from masking weak signals; 0.15psRMS jitter maintains EVM <1.5% at 256-QAM. |
Use Scenario: Real-time spectrum analysis and adaptive waveform generation in field-deployable military/commercial SDR platforms. IC Role / Device Role / Timing Role: High-fidelity front-end digitizer supporting reconfigurable bandwidth (5–140MHz) and dynamic range scaling via SENSE pin. Use Value: 73.1dB SNR enables detection of –120dBm signals in presence of +10dBm blockers; 125Msps rate supports 60MHz instantaneous bandwidth. |
| Portable Medical Imaging | Multichannel Data Acquisition |
|
Use Scenario: Ultrasound beamformer digitizing echo returns from 64+ transducer elements in handheld imaging probes. IC Role / Device Role / Timing Role: Low-power, time-coherent quad ADC capturing RF echoes with matched gain/offset across channels for synthetic aperture processing. Use Value: ±0.2%FS gain matching and ±3mV offset matching ensure <0.1dB amplitude error across channels; 558mW total power enables battery operation. |
Use Scenario: High-precision vibration monitoring in industrial predictive maintenance systems using multi-axis accelerometer arrays. IC Role / Device Role / Timing Role: Simultaneous sampling of four sensor channels with 14-bit resolution and 800MHz input bandwidth for transient event capture. Use Value: 1.2LSBRMS transition noise and no missing codes preserve fidelity of microsecond-scale shock pulses; SPI configuration enables runtime calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9694BCPZ-1300 | 14-bit, 1.3Gsps, JESD204B interface, higher power (2.4W), 72dB SNR at 1GHz input | Targets mmWave 5G and radar requiring >1Gsps; incompatible pinout and interface protocol | Select for >1Gsps sampling; avoid for cost-sensitive, low-power, LVDS-based designs. |
| LTC2173CUKG-14#PBF | Same family, 80Msps, 376mW, identical pinout and register map, lower SNR (72.6dB at 70MHz) | Drop-in replacement for lower-speed applications where 125Msps headroom is unnecessary | Choose for power-constrained systems needing same footprint and firmware compatibility at reduced speed. |
Compared with AD9694BCPZ-1300, LTC2175CUKG-14#PBF offers superior power efficiency (558mW vs. 2400mW) and LVDS simplicity but lacks JESD204B scalability; compared with LTC2173CUKG-14#PBF, it delivers 45Msps higher throughput and 0.5dB better SNR at the cost of +182mW power, making it optimal for mid-band 5G and SDR front ends.
Availability
LTC2175CUKG-14#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio development, and portable medical imaging systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC2175CUKG-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving communications, industrial, automotive, and healthcare markets.
The LTC2175CUKG-14#PBF belongs to ADI's high-speed precision ADC product line, designed specifically for RF/IF digitization in communications infrastructure and instrumentation where dynamic range, jitter, and multichannel coherence are critical.
FAQ
What is the maximum sampling rate supported by the LTC2175CUKG-14#PBF?
The LTC2175CUKG-14#PBF supports a maximum sampling rate of 125Msps, as confirmed in its Absolute Maximum Ratings and Dynamic Accuracy specifications. This rate is achievable with 2-lane LVDS serialization and 1.8V supplies. At 125Msps, the device maintains 73.1dB SNR and 88dB SFDR at 70MHz input frequency, making it suitable for high-bandwidth IF sampling applications. Lower rates (e.g., 105Msps or 80Msps) correspond to the pin-compatible LTC2174 and LTC2173 variants.
Does the LTC2175CUKG-14#PBF support both internal and external voltage references?
Yes, the LTC2175CUKG-14#PBF supports both internal and external reference configurations. The SENSE pin (Pin 50) selects the mode: tied to VDD enables the internal 1.25V reference with ±25ppm/°C drift and ±1V input range; tied to GND selects ±0.5V range; applying 0.625–1.3V to SENSE configures an external reference with ±0.8×VSENSE input range. Internal reference specs include 1.225–1.275V output and 7Ω output resistance.
How many LVDS data lanes does the LTC2175CUKG-14#PBF use, and how is serialization configured?
The LTC2175CUKG-14#PBF supports both 1-lane and 2-lane LVDS serialization modes. In 2-lane mode, each channel outputs two bits per sample (e.g., OUT1A+/OUT1A– and OUT1B+/OUT1B–), reducing interface width. In 1-lane mode, only OUT1A+/OUT1A– is active per channel, halving data rate but simplifying routing. Mode selection is controlled via the CS pin in parallel programming mode (PAR/SER = VDD), with SCK setting output current.
What power-saving modes are available on the LTC2175CUKG-14#PBF, and what are their typical power draws?
The LTC2175CUKG-14#PBF offers Nap Mode (85mW) and Sleep Mode (1mW), both accessible via SPI register writes or parallel control pins. Nap Mode retains configuration and enables fast wake-up (<1µs), while Sleep Mode shuts down most circuitry for minimal quiescent draw. Full operation consumes 558mW at 125Msps (2-lane, 1.75mA mode), with analog (283mA) and digital (27mA) supply currents separately specified.
Is the LTC2175CUKG-14#PBF pin-compatible with other members of the LTC217x-14 family?
Yes, the LTC2175CUKG-14#PBF is pin-compatible with the LTC2174CUKG-14#PBF and LTC2173CUKG-14#PBF, sharing identical 52-pin QFN packaging, pin functions, and register maps. This allows hardware reuse across speed grades (125/105/80Msps) and simplifies design migration. Differences are limited to AC performance (e.g., SNR degrades from 73.1dB to 72.6dB to 72.5dB) and power (558mW → 450mW → 376mW), with no changes to pinout or interface logic.
LTC2175CUKG-14#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 125M
- Number of Inputs:
- 4
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 4
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 52-QFN (7x8)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2175CUKG-14#PBF FAQ
1.How can I place an order for LTC2175CUKG-14#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2175CUKG-14#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2175CUKG-14#PBF reliable?
The price and inventory of LTC2175CUKG-14#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2175CUKG-14#PBF is usually 5 days.
3.What payment methods are accepted for LTC2175CUKG-14#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2175CUKG-14#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2175CUKG-14#PBF?
LTC2175CUKG-14#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2175CUKG-14#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2175CUKG-14#PBF?
For technical support, including LTC2175CUKG-14#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2175CUKG-14#PBF requirements.
6.How does Aetrix verify that LTC2175CUKG-14#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2175CUKG-14#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2175CUKG-14#PBF meets industry standards.
7.What is the process for return or replacement of LTC2175CUKG-14#PBF?
All LTC2175CUKG-14#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2175CUKG-14#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2175CUKG-14#PBF part is unused and in its original packaging.
Return procedure for LTC2175CUKG-14#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2175CUKG-14#PBF Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

