Analog Devices Inc. LTC2182CUP#PBF
- Part No.:
- LTC2182CUP#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LTC2182CUP#PBF.pdf
- Description:
- IC ADC 16BIT PIPELINED 64QFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,021
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2182CUP#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, 65Msps dual-channel simultaneous-sampling analog-to-digital converter optimized for high-dynamic-range signal digitization in communications infrastructure. It delivers 77dB SNR, 90dB SFDR, and ultralow 0.07psRMS aperture jitter, enabling undersampling of IF signals up to 140MHz in cellular base stations and software-defined radios.
For engineers reviewing the LTC2182CUP#PBF datasheet, LTC2182CUP#PBF pinout, LTC2182CUP#PBF application, or LTC2182CUP#PBF equivalent, key selection factors include its 64-pin QFN package, 1.8V single-supply operation, selectable CMOS/DDR-CMOS/DDR-LVDS output interfaces, and support for differential or single-ended clock inputs with duty cycle stabilization.
Technical Context
The LTC2182CUP#PBF implements two independent 16-bit ADC cores sharing a common sample-and-hold with 550MHz full-power bandwidth, enabling true simultaneous sampling across channels. Its internal reference provides 1.25V ±25ppm/°C stability, while external reference mode supports SENSE pin input from 0.625V to 1.3V.
Digital interface flexibility includes serial SPI configuration, programmable output data format (two's complement or offset binary), optional data randomization to reduce spectral spurs, and low-power Nap (10mW) and Sleep (1mW) modes. Clock encoding supports both differential (ENC+/ENC–) and single-ended (ENC+ only) operation with configurable timing constraints.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in precision measurement systems. |
| Sampling Rate | 65Msps - enables real-time digitization of wideband IF signals up to 140MHz using undersampling techniques. |
| SNR | 77dB at 70MHz input - ensures high-fidelity signal reconstruction in demanding RF receiver chains. |
| SFDR | 90dB at 70MHz input - suppresses harmonic distortion critical for multi-carrier cellular and radar applications. |
| Aperture Jitter | 0.07psRMS - minimizes sampling uncertainty, directly enabling high-IF sampling without external jitter cleanup. |
| Power Dissipation | 160mW total at 65Msps with CMOS outputs - balances performance and thermal management in dense PCB layouts. |
| Analog Supply | Single 1.8V (1.7V–1.9V) - simplifies power delivery and reduces board-level DC-DC complexity. |
Pinout & Package
64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (1,16,17,64) | Analog power supply | 1.7V–1.9V supply for ADC core; requires local 0.1µF ceramic bypassing per group. |
| AIN1+/AIN1– (4,5) | Channel 1 differential analog input | Accepts 1VP-P to 2VP-P differential signal; biased by VCM1 (Pin 2) at VDD/2. |
| ENC+/ENC– (18,19) | Differential encode clock input | Rising edge on ENC+ initiates conversion; ENC– tied to GND enables single-ended mode. |
| D1_0–D1_15 / D2_0–D2_15 (43–58,23–32) | Parallel digital outputs | Configurable as full-rate CMOS, DDR-CMOS, or DDR-LVDS; OVDD (Pin 42) sets output swing. |
| PAR/SER (11) | Programming mode select | Ground = serial SPI control (CS/SCK/SDI/SDO); VDD = parallel logic control of key functions. |
Key Features
| Feature | Design Value |
|---|---|
| Simultaneous sampling dual-channel architecture | Eliminates channel-to-channel skew for coherent I/Q demodulation and beamforming in phased-array systems. |
| Optional clock duty cycle stabilizer | Enables full-speed operation with non-50% clock duty cycles, relaxing clock generation requirements in FPGA-based systems. |
| Selectable output interface | Supports CMOS, DDR-CMOS, or DDR-LVDS - allows optimization for PCB routing density, EMI, and FPGA interface compatibility. |
| Programmable input range | 1VP-P to 2VP-P differential range selection via REFH/REFL pins - matches varying signal chain gain stages without external attenuation. |
| Low-power Nap and Sleep modes | Reduces power to 10mW (Nap) or 1mW (Sleep) - extends battery life in portable medical imaging and handheld test equipment. |
Applications
| Cellular Base Stations | Software Defined Radios |
|---|---|
Use Scenario: Digitizing multiple RF receive paths in LTE/5G macrocell and small-cell transceivers. IC Role / Device Role / Timing Role: Dual-channel ADC captures synchronized I/Q data streams for digital predistortion and MIMO processing. Use Value: 77dB SNR and 90dB SFDR maintain EVM compliance across wide modulation bandwidths up to 100MHz. | Use Scenario: Reconfigurable front-end for military comms, spectrum monitoring, and cognitive radio platforms. IC Role / Device Role / Timing Role: Simultaneous sampling ADC enables real-time frequency agility and wide instantaneous bandwidth capture. Use Value: 550MHz full-power bandwidth and 0.07psRMS jitter support direct IF sampling at 300MHz+ center frequencies. |
| Portable Medical Imaging | Multi-Channel Data Acquisition |
Use Scenario: Ultrasound beamformer digitizing echo returns from 128+ transducer elements. IC Role / Device Role / Timing Role: Dual ADC channels acquire time-aligned RF echoes for synthetic aperture processing. Use Value: 16-bit resolution with ±2LSB INL preserves tissue contrast and dynamic range in B-mode imaging. | Use Scenario: High-precision test equipment capturing transient waveforms across multiple sensors simultaneously. IC Role / Device Role / Timing Role: Simultaneous sampling ADC ensures phase-coherent acquisition for FFT-based vibration analysis. Use Value: Channel matching (±0.3%FS gain, ±1.5mV offset) eliminates calibration drift between measurement channels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 16-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9269BCPZ-65 | 65Msps, 16-bit, single-channel; requires external clock distribution for dual-channel sync. | Lacks native simultaneous sampling; needs external circuitry for channel alignment. | Choose when system already uses ADI ecosystem and channel count can be met with two separate converters. |
| ADS52J90IRGCT | 65Msps, 16-bit, 8-channel; lower SNR (74dB) and higher power (540mW). | Higher channel density but reduced dynamic range and increased thermal load. | Prefer for multi-channel systems where board space is constrained and SNR >75dB is acceptable. |
Compared with AD9269BCPZ-65 and ADS52J90IRGCT, the LTC2182CUP#PBF uniquely integrates true simultaneous sampling, lower power (160mW), and superior SFDR (90dB), making it optimal for phase-sensitive, power-constrained dual-channel applications like portable ultrasound and compact SDRs.
Availability
LTC2182CUP#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, software-defined radio development, and portable medical imaging requiring stable component supply and long-term production continuity.
Supply support for LTC2182CUP#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2182CUP#PBF belongs to ADI's high-speed precision ADC product line, designed specifically for demanding communications and instrumentation applications requiring simultaneous sampling, low jitter, and flexible digital interfacing.
FAQ
What is the operating temperature range for the LTC2182CUP#PBF?
The LTC2182CUP#PBF is specified for commercial-grade operation from 0°C to 70°C. This is indicated by the "C" suffix in the part number and confirmed in the Absolute Maximum Ratings table. For extended temperature operation (–40°C to 85°C), the LTC2182IUP#PBF variant is available.
Does the LTC2182CUP#PBF support external voltage reference?
Yes, the LTC2182CUP#PBF supports external reference mode via the SENSE pin (Pin 63), which accepts an input from 0.625V to 1.3V. When used, the internal 1.25V reference is disabled, allowing precise system-level reference control and improved temperature stability when paired with a high-accuracy external source.
How does the PAR/SER pin affect configuration of the LTC2182CUP#PBF?
The PAR/SER pin (Pin 11) selects programming mode: grounded for serial SPI control (using CS/SCK/SDI/SDO), or tied to VDD for parallel logic control. In serial mode, all device features-including output format, randomizer, and duty cycle stabilizer-are fully configurable; parallel mode offers limited control over key functions only.
What output interface options does the LTC2182CUP#PBF support?
The LTC2182CUP#PBF supports three digital output modes: full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS. Output voltage levels are set by OVDD (Pin 42), which can be 1.2V, 1.5V, or 1.8V for CMOS modes, or 1.7V–1.9V for LVDS mode with integrated 100Ω termination.
Can the LTC2182CUP#PBF operate with a single-ended clock input?
Yes, the LTC2182CUP#PBF supports single-ended clock operation by tying ENC– (Pin 19) to GND and driving ENC+ (Pin 18) with a 1.8V square wave. The datasheet specifies VIH ≥1.2V and VIL ≤0.6V for reliable single-ended encoding at 65Msps, with timing parameters validated under this configuration.
LTC2182CUP#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 65M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 64-QFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2182CUP#PBF FAQ
1.How can I place an order for LTC2182CUP#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2182CUP#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2182CUP#PBF reliable?
The price and inventory of LTC2182CUP#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2182CUP#PBF is usually 5 days.
3.What payment methods are accepted for LTC2182CUP#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2182CUP#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2182CUP#PBF?
LTC2182CUP#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2182CUP#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2182CUP#PBF?
For technical support, including LTC2182CUP#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2182CUP#PBF requirements.
6.How does Aetrix verify that LTC2182CUP#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2182CUP#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2182CUP#PBF meets industry standards.
7.What is the process for return or replacement of LTC2182CUP#PBF?
All LTC2182CUP#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2182CUP#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2182CUP#PBF part is unused and in its original packaging.
Return procedure for LTC2182CUP#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2182CUP#PBF Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

