Analog Devices Inc. LTC2183CUP#PBF

Overview

LTC2183CUP#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, dual-channel simultaneous-sampling analog-to-digital converter with 80Msps sampling rate, 76.6dB SNR, and 90dB SFDR. It operates from a single 1.8V supply, supports CMOS/DDR-CMOS/DDR-LVDS outputs, and targets high-fidelity signal digitization in portable medical imaging and multi-channel data acquisition systems.

For engineers reviewing the LTC2183CUP#PBF datasheet, LTC2183CUP#PBF pinout, LTC2183CUP#PBF application, or LTC2183CUP#PBF equivalent, key selection criteria include its 80Msps dual-channel throughput, 550MHz full-power bandwidth, low 200mW total power dissipation, and support for differential encode inputs with optional duty cycle stabilization.

Technical Context

The LTC2183CUP#PBF implements two independent 16-bit ADC cores with shared sample-and-hold circuitry, enabling true simultaneous sampling across channels. Its ultralow 0.09psRMS jitter enables undersampling of IF signals up to 140MHz while maintaining 76.6dB SNR at 80Msps.

It features configurable digital output interfaces (full-rate CMOS, DDR-CMOS, or DDR-LVDS), selectable input ranges (1VP-P to 2VP-P), and on-chip reference buffers (VCM1/VCM2, REFH/REFL). Serial SPI configuration and low-power modes (Nap: 16mW, Sleep: 1mW) support flexible system integration.

Key Specifications

Pinout & Package

64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND, must be soldered to PCB). Package supports high-density layout and efficient thermal management in space-constrained designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel 16-bit ADC applications.

Compared with AD9269-80EBZ and ADS52J90IRGCT, the LTC2183CUP#PBF offers integrated VCM generation, single 1.8V supply operation, and flexible parallel output modes - simplifying power delivery and interface design for portable and embedded instrumentation.

Availability

LTC2183CUP#PBF is available at Aetrix Electronics and suitable for portable medical imaging, multi-channel data acquisition, nondestructive testing, and software defined radio applications requiring stable component supply and long-term production continuity.

Supply support for LTC2183CUP#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies.

The LTC2183CUP#PBF belongs to the LTC218x family of ultra-low-jitter dual-channel ADCs designed specifically for demanding communications and instrumentation applications requiring simultaneous sampling, wide bandwidth, and low power.

FAQ

What is the maximum sampling rate supported by the LTC2183CUP#PBF?

The LTC2183CUP#PBF supports a maximum sampling rate of 80Msps across both channels simultaneously. This rate is fixed for the LTC2183 variant (as opposed to the LTC2184 at 105Msps and LTC2185 at 125Msps), and is specified over the full 0°C to 70°C operating temperature range with guaranteed performance including 76.6dB SNR and 90dB SFDR at 70MHz input frequency.

Does the LTC2183CUP#PBF require external reference components?

No, the LTC2183CUP#PBF includes internal reference buffers (VCM1, VCM2, REFH, REFL) that provide stable common-mode bias and reference voltages. When using the internal reference, only standard 0.1µF ceramic bypass capacitors on REFH/REFL are required. An external voltage can be applied to the SENSE pin (0.625V–1.3V) to override the internal reference for custom full-scale adjustment, but this is optional.

How does the power consumption of the LTC2183CUP#PBF compare across output modes?

In CMOS output modes (full-rate or DDR), the LTC2183CUP#PBF dissipates 200mW total at 80Msps with 1.8V VDD and 1.2V OVDD. In DDR-LVDS mode with 3.5mA output current, power increases to 382mW. The device also supports Nap mode (16mW) and Sleep mode (1mW) for dynamic power scaling - all values are measured under sine-wave input conditions per the official datasheet specifications for the LTC2183CUP#PBF.

Can the LTC2183CUP#PBF interface directly with an FPGA using LVDS signaling?

Yes, the LTC2183CUP#PBF supports DDR-LVDS output mode with on-chip 100Ω termination and programmable output current (1.75mA or 3.5mA). Its D1_x and D2_x differential pairs (e.g., D1_0_1+, D1_0_1–) meet standard LVDS electrical specifications, enabling direct connection to FPGA LVDS input banks without external termination resistors - provided the FPGA supports DDR capture and the 64-pin QFN layout accommodates matched-length differential routing.

What is the function of the PAR/SER pin on the LTC2183CUP#PBF?

The PAR/SER pin on the LTC2183CUP#PBF selects between Serial Programming Mode (grounded) and Parallel Programming Mode (tied to VDD). In Serial mode, CS/SCK/SDI/SDO form an SPI interface for full register control. In Parallel mode, those pins become direct logic inputs controlling basic functions like output format and power modes - offering simpler, faster configuration at the cost of reduced feature access. The pin must be hard-wired, not driven dynamically.