Analog Devices Inc. LTC2183IUP#PBF

Overview

LTC2183IUP#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, dual-channel simultaneous-sampling analog-to-digital converter with 80Msps sampling rate, 76.6dB SNR, and 90dB SFDR. It operates from a single 1.8V supply, supports CMOS/DDR CMOS/DDR LVDS outputs, and targets high-fidelity signal digitization in portable medical imaging and multi-channel data acquisition systems.

For engineers reviewing the LTC2183IUP#PBF datasheet, LTC2183IUP#PBF pinout, LTC2183IUP#PBF application, or LTC2183IUP#PBF equivalent, key selection factors include its guaranteed ±2LSB INL over temperature, 550MHz full-power bandwidth, optional clock duty cycle stabilizer, and support for differential or single-ended encode inputs - all critical for undersampling IF signals in SDR and base station front-ends.

Technical Context

The LTC2183IUP#PBF implements two independent 16-bit ADC cores with shared sample-and-hold, enabling true simultaneous sampling across channels. Its ultralow 0.09psRMS jitter (differential encode) and 3.2LSBRMS transition noise ensure high-fidelity digitization of wideband RF/IF signals up to 140MHz input frequency.

It features configurable digital output interfaces - full-rate CMOS, DDR CMOS, or DDR LVDS - with separate OVDD supply (1.1V–1.9V) allowing level-shifting. Internal reference (1.25V ±25ppm/°C) and external reference modes are supported via the SENSE pin, with VREF output capable of sourcing/sinking ±400µA.

Key Specifications

Pinout & Package

64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND, must be soldered). Pin functions are mode-dependent (CMOS vs LVDS); LVDS mode uses differential pairs (e.g., D1_0_1+, D1_0_1–), while CMOS mode uses single-ended pins (e.g., D1_0, D1_1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel 16-bit ADC applications.

Compared with AD9269-80EBZ and ADS52J90IRGCT, the LTC2183IUP#PBF delivers native dual-channel simultaneity with lower power (200mW vs ≥350mW), simpler parallel interfacing, and superior jitter performance - making it optimal for portable, phase-critical, and thermally constrained applications.

Availability

LTC2183IUP#PBF is available at Aetrix Electronics and suitable for portable medical imaging, multi-channel data acquisition, and cellular base station monitoring requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature grade (–40°C to +85°C).

Supply support for LTC2183IUP#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2183IUP#PBF belongs to the LTC218x family of ultra-low-jitter dual ADCs designed specifically for demanding communications and instrumentation applications where simultaneous sampling, wide input bandwidth, and exceptional dynamic range are mandatory.

FAQ

What is the operating temperature range for the LTC2183IUP#PBF?

The LTC2183IUP#PBF is rated for industrial temperature operation from –40°C to +85°C, as indicated by the "I" grade suffix in the part number. This range is validated across all electrical specifications including INL, SNR, and SFDR, making it suitable for deployment in outdoor base stations and field-portable medical devices where ambient temperatures vary widely.

Does the LTC2183IUP#PBF support external reference voltage?

Yes, the LTC2183IUP#PBF supports external reference voltage via the SENSE pin (Pin 63), which accepts 0.625V to 1.3V. When used, the internal 1.25V reference is disabled, and the ADC full-scale range scales proportionally - enabling ratiometric measurements with external sensors or precision voltage references for improved system-level accuracy.

How does the clock duty cycle stabilizer function in the LTC2183IUP#PBF?

The clock duty cycle stabilizer in the LTC2183IUP#PBF is an internal circuit that corrects non-50% duty cycle clocks before they reach the ADC core. Enabled via SPI register, it allows reliable operation with clocks having 30%–70% duty cycle - eliminating the need for external duty-cycle correction ICs when using crystal oscillators or PLLs with asymmetric output.

What digital output formats does the LTC2183IUP#PBF support?

The LTC2183IUP#PBF supports three digital output formats: full-rate CMOS, double-data-rate (DDR) CMOS, and DDR LVDS. Format selection is controlled by the PAR/SER pin and SPI configuration registers. CMOS outputs use single-ended pins (e.g., D1_0–D1_15) with OVDD-supplied swing (1.2V–1.8V); LVDS outputs use differential pairs (e.g., D1_0_1+, D1_0_1–) with internal 100Ω termination.

Can the LTC2183IUP#PBF operate with single-ended analog inputs?

No - the LTC2183IUP#PBF requires differential analog inputs (AIN1+/AIN1–, AIN2+/AIN2–) for specified performance. However, single-ended encode clock inputs are supported by tying ENC– to GND. For single-ended analog sources, external baluns or fully differential amplifiers (e.g., LTC6409) must be used to convert the signal prior to the ADC inputs to maintain SNR and SFDR specifications.