Analog Devices Inc. LTC2195IUKG#TRPBF
- Part No.:
- LTC2195IUKG#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 52-WFQFN Exposed Pad
- Datasheet:
-
LTC2195IUKG#TRPBF.pdf
- Description:
- IC ADC 16BIT PIPELINED 52QFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,695
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Product details
Overview
LTC2195IUKG#TRPBF from Analog Devices (formerly Linear Technology) is a 16-bit, dual-channel, simultaneous-sampling analog-to-digital converter optimized for high-frequency, wide-dynamic-range signal digitization in communications infrastructure. It delivers 76.8dB SNR, 90dB SFDR, and ultralow 0.07psRMS jitter at 125Msps, enabling undersampling of IF signals up to 140MHz in cellular base stations and software-defined radios.
For engineers reviewing the LTC2195IUKG#TRPBF datasheet, LTC2195IUKG#TRPBF pinout, LTC2195IUKG#TRPBF application, or LTC2195IUKG#TRPBF equivalent, this page provides verified technical context, serial LVDS interface timing, dual-channel INL/DNL specs, low-power 1.8V operation, and QFN-52 package layout - all critical for RF receiver front-end and multi-channel data acquisition design validation.
Technical Context
The LTC2195IUKG#TRPBF integrates two independent 16-bit ADC cores with shared clock domain and synchronized sampling, supporting differential analog inputs (1–2VP-P range), internal/external reference selection via SENSE pin, and programmable LVDS serialization (1/2/4 bits per channel). Its 550MHz full-power bandwidth sample-and-hold enables direct RF sampling in sub-6GHz bands.
It features an on-chip duty cycle stabilizer for encode inputs, SPI-configurable output modes (including shutdown/nap), and LVDS drivers with selectable 1.75mA/3.5mA current and optional 100Ω internal termination - ensuring robust signal integrity across PCB traces without external resistors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit with no missing codes over –40°C to +85°C - guarantees monotonicity in precision measurement systems. |
| Sampling Rate | 125Msps maximum - supports Nyquist sampling of signals up to 62.5MHz or undersampling of IFs up to 140MHz. |
| SNR / SFDR | 76.8dB SNR and 90dB SFDR at 70MHz input - enables high-fidelity digitization in demanding comms receivers. |
| Jitter Performance | 0.07psRMS aperture jitter - minimizes noise floor degradation when undersampling high-frequency carriers. |
| Power Consumption | 432mW total at 125Msps (216mW per channel) - enables thermal-efficient dual-channel digitization in compact RF modules. |
| Analog Supply | Single 1.8V (VDD = 1.7–1.9V) - simplifies power delivery and reduces board-level DC/DC count in battery-powered or space-constrained designs. |
| Digital Interface | Serial LVDS outputs with 1/2/4-bit per channel configuration - reduces pin count vs parallel interfaces while maintaining EMI resilience. |
Pinout & Package
Package: 52-lead (7mm × 8mm) plastic QFN with exposed thermal pad (Pin 53 = GND), requiring soldering to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCM1 (Pin 1) | Channel 1 common-mode bias output | Nominally VDD/2; used to set AIN1± common-mode voltage - requires 0.1µF bypass to GND. |
| AIN1+/AIN1– (Pins 3/4) | Channel 1 differential analog input | Accepts 1–2VP-P differential signal; CMRR = 80dB ensures rejection of noise coupled to both inputs. |
| ENC+/ENC– (Pins 17/18) | Differential encode clock input | Supports PECL/LVDS/TTL/CMOS; internal duty cycle stabilizer maintains performance across 2–100% duty cycles. |
| OUT1A+/OUT1A– (Pins 43/44) | Channel 1 LVDS serial data output (lane A) | Configurable 1.75mA/3.5mA drive strength; internal 100Ω termination option eliminates external resistors. |
| FR+/FR– (Pins 31/32) | Frame start indicator outputs | Synchronizes data frames across both channels - essential for time-aligned dual-channel processing. |
| SDO (Pin 46) | Serial data output / LVDS current select | In serial mode: readback of SPI registers; in parallel mode: selects 1.75mA vs 3.5mA LVDS output current. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel simultaneous sampling | Guarantees precise time alignment between channels - critical for I/Q demodulation and beamforming applications. |
| Programmable LVDS serialization | 1/2/4-bit per channel reduces interface width by up to 4× vs parallel LVDS - saves PCB routing layers and FPGA I/O resources. |
| Internal clock duty cycle stabilizer | Enables full-speed operation with non-50% clock sources - eliminates need for external clock conditioners in legacy system upgrades. |
| Low-power sleep/nap modes | 1mW sleep and 50mW nap power states - extends operational life in portable medical imaging and battery-backed test equipment. |
| Flexible reference architecture | Internal 1.25V reference or external 0.625–1.3V via SENSE pin - supports ±0.5V to ±1.6V input ranges without external amplifiers. |
Applications
| Cellular Base Stations | Software-Defined Radios |
|---|---|
|
Use Scenario: Digitizing dual-path IF signals (e.g., 70MHz/69MHz 2-tone) in macrocell remote radio heads. IC Role / Device Role / Timing Role: Dual-channel ADC core providing synchronized sampling with <0.1ps jitter for coherent MIMO processing. Use Value: 90dB SFDR prevents intermodulation distortion masking adjacent channels in LTE/5G FDD deployments. |
Use Scenario: Real-time spectrum analysis and adaptive waveform reception in field-deployable SDR platforms. IC Role / Device Role / Timing Role: High-linearity ADC front-end enabling reconfigurable bandwidth (up to 125Msps) and dynamic range adaptation. Use Value: 76.8dB SNR preserves signal fidelity across 140MHz instantaneous bandwidth - essential for wideband modulation analysis. |
| Portable Medical Imaging | Multi-Channel Data Acquisition |
|
Use Scenario: Ultrasound beamformer digitization in handheld echocardiography devices with tight thermal constraints. IC Role / Device Role / Timing Role: Low-power dual ADC delivering 16-bit resolution at 80–125Msps with minimal self-heating. Use Value: 432mW total power at 125Msps enables fanless operation and extended battery runtime in Class II medical devices. |
Use Scenario: Simultaneous capture of vibration, temperature, and acoustic signatures in industrial predictive maintenance sensors. IC Role / Device Role / Timing Role: Precision dual-channel sampling with ±2LSB INL and no missing codes across –40°C to +85°C. Use Value: Guaranteed monotonicity and <1.5mV offset matching ensure accurate cross-channel correlation for FFT-based fault detection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9680BCPZ-500 | 14-bit, 500Msps, JESD204B interface, higher power (1.5W), wider bandwidth (1.5GHz) | Targets higher-speed radar and wideband instrumentation - not drop-in due to interface and supply differences | Select when >125Msps sampling or JESD204B backplane integration is required; verify layout changes for 1.5V analog/1.8V digital supplies. |
| LTC2268IUKG#TRPBF | 16-bit, 80Msps, same QFN-52 package, lower power (249mW), no internal duty cycle stabilizer | Optimized for lower-frequency, ultra-low-power applications like portable spectrum analyzers | Choose for cost-sensitive, thermally constrained designs where 80Msps suffices and encode clock conditioning is handled externally. |
Compared with AD9680BCPZ-500 and LTC2268IUKG#TRPBF, the LTC2195IUKG#TRPBF uniquely balances 125Msps speed, 16-bit resolution, sub-0.1ps jitter, and 432mW power in a single 1.8V supply - making it optimal for mid-band RF digitization where JESD204B complexity is unnecessary.
Availability
LTC2195IUKG#TRPBF is available at Aetrix Electronics and suitable for cellular base stations, software-defined radios, and portable medical imaging systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC2195IUKG#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance signal chain portfolio, emphasizing precision, speed, and power efficiency for demanding analog applications.
The LTC2195IUKG#TRPBF belongs to Linear's ultra-low-jitter, dual-channel ADC family designed specifically for communications infrastructure and high-fidelity data acquisition - where simultaneous sampling, SFDR, and thermal stability are non-negotiable.
FAQ
What is the operating temperature range of the LTC2195IUKG#TRPBF?
The LTC2195IUKG#TRPBF is rated for industrial operation from –40°C to +85°C (I-grade), validated across all specifications including INL (±2LSB typ), SNR (76.8dB), and power consumption (432mW at 125Msps). This range ensures reliability in outdoor base station enclosures and portable medical equipment exposed to ambient thermal cycling.
Does the LTC2195IUKG#TRPBF support external reference input?
Yes, the LTC2195IUKG#TRPBF supports external reference input via the SENSE pin (Pin 50). Applying 0.625V–1.3V to SENSE sets the input range to ±0.8 × VSENSE, enabling flexible scaling (e.g., ±0.8V for 1.6VP-P). Internal reference mode (1.25V) is selected by tying SENSE to VDD or GND for ±1V or ±0.5V ranges respectively.
How many LVDS data lanes does the LTC2195IUKG#TRPBF support per channel?
The LTC2195IUKG#TRPBF supports three LVDS serialization modes per channel: 1-lane (1 bit per clock edge), 2-lane (2 bits per edge), or 4-lane (4 bits per edge). Mode selection is configured via CS/SCK in parallel programming mode or SPI register writes in serial mode - allowing trade-offs between data rate, FPGA I/O usage, and PCB routing density.
What is the function of the FR+ and FR– pins on the LTC2195IUKG#TRPBF?
The FR+ and FR– pins (Pins 31/32) are differential frame start outputs that assert a pulse at the beginning of each data frame. They align with the first valid sample of each conversion cycle and are active simultaneously for both channels - enabling precise synchronization of downstream DSP blocks, such as FFT engines or digital downconverters, across dual-channel paths.
Can the LTC2195IUKG#TRPBF operate with a single-ended encode clock?
Yes, the LTC2195IUKG#TRPBF supports single-ended encode operation by tying ENC– (Pin 18) to GND and driving ENC+ (Pin 17) with a 1.8V square wave. In this mode, jitter increases slightly to 0.09psRMS, but full 125Msps operation remains supported - useful for legacy clock sources lacking differential capability.
LTC2195IUKG#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 52-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 125M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 52-QFN (7x8)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2195IUKG#TRPBF FAQ
1.How can I place an order for LTC2195IUKG#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2195IUKG#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2195IUKG#TRPBF reliable?
The price and inventory of LTC2195IUKG#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2195IUKG#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2195IUKG#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2195IUKG#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2195IUKG#TRPBF?
LTC2195IUKG#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2195IUKG#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2195IUKG#TRPBF?
For technical support, including LTC2195IUKG#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2195IUKG#TRPBF requirements.
6.How does Aetrix verify that LTC2195IUKG#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2195IUKG#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2195IUKG#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2195IUKG#TRPBF?
All LTC2195IUKG#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2195IUKG#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2195IUKG#TRPBF part is unused and in its original packaging.
Return procedure for LTC2195IUKG#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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