Analog Devices Inc. LTC2229CUH#PBF
- Part No.:
- LTC2229CUH#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LTC2229CUH#PBF.pdf
- Description:
- IC ADC 12BIT PIPELINED 32QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,119
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Product details
Overview
LTC2229CUH#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 80Msps low-power pipelined analog-to-digital converter optimized for high-frequency signal digitization in imaging and communications systems. It operates from a single 3V supply (2.7V–3.4V), delivers 70.6dB SNR and 90dB SFDR at 70MHz input, features 575MHz full-power bandwidth, and supports flexible ±0.5V to ±1V differential input ranges via SENSE pin configuration.
For engineers reviewing the LTC2229CUH#PBF datasheet, LTC2229CUH#PBF pinout, LTC2229CUH#PBF application, or LTC2229CUH#PBF equivalent, key selection considerations include its 32-pin QFN package, clock duty cycle stabilizer, shutdown/nap modes, 0.3LSBRMS transition noise, and compatibility with 1.5V VCM-biased differential front ends for ultrasound and spectral analysis systems.
Technical Context
The LTC2229CUH#PBF implements a six-stage CMOS pipelined ADC architecture with 5-cycle latency and integrated sample-and-hold featuring 575MHz full-power bandwidth. Its internal 1.5V bandgap reference drives VCM output and enables programmable input ranges via SENSE pin voltage selection (VCM = ±0.5V range; VDD = ±1V range).
It uses a single-ended CLK input with optional duty cycle stabilizer to maintain AC performance across wide duty cycle variations, and supports offset binary or 2's complement output formats selected by MODE pin voltage. Digital outputs are driven by separate OVDD (0.5V–3.6V) to interface with diverse logic families.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in closed-loop control or precision measurement. |
| Sample Rate | 80Msps - supports Nyquist-limited bandwidth up to 40MHz or undersampled RF signals beyond 100MHz using aliasing techniques. |
| SNR @ 70MHz | 70.6dBFS - enables >11.4 effective bits for high-fidelity digitization of wideband communication carriers or medical ultrasound echoes. |
| SFDR @ 70MHz | 90dBc (2nd/3rd harmonic) - suppresses spurious content critical for detecting weak signals adjacent to strong interferers in spectral analysis. |
| Power Dissipation | 211mW at 80Msps - achieves 2.64mW per Msps efficiency, reducing thermal load in portable instrumentation and densely packed FPGA-based receivers. |
| Input Bandwidth | 575MHz - preserves amplitude and phase integrity of fast-rising pulses and wideband modulated signals without external anti-alias filtering below ~200MHz. |
| INL / DNL | ±0.4LSB typ / ±0.2LSB typ - ensures accurate amplitude linearity for calibrated imaging systems and digital beamforming applications. |
Pinout & Package
Package: 32-lead (5mm × 5mm) plastic QFN with exposed pad (Pin 33 = GND). Exposed pad must be soldered to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN+, AIN− | Differential analog input | Accepts ±0.5V or ±1V differential swing centered at 1.5V (VCM); high common-mode rejection (>80dB) minimizes noise coupling in transformer-coupled front ends. |
| REFH, REFL | ADC reference terminals | Internally generated high/low reference pair; require local 0.1µF + 2.2µF bypassing to stabilize reference settling and reduce noise-induced quantization error. |
| VDD (Pins 7, 32) | Analog supply | Single 2.7V–3.4V rail powers analog core and S/H; tight regulation (<±50mV) required to avoid gain drift and SNR degradation. |
| CLK | Sampling clock input | Single-ended CMOS/TTL-compatible; aperture jitter ≤0.2psRMS enables <70dB SNR at 140MHz input when driven with low-phase-noise source. |
| SHDN, OE | Power mode control | Combination controls functional states: SHDN=L/OE=L = active; SHDN=H/OE=L = nap mode (15mW); SHDN=H/OE=H = shutdown (2mW). |
| MODE | Output format & DCS select | Voltage-selectable: GND = offset binary + DCS off; 1/3VDD = offset binary + DCS on; 2/3VDD = 2's complement + DCS on; VDD = 2's complement + DCS off. |
| SENSE | Input range programming | Direct connection to VCM selects ±0.5V range; to VDD selects ±1V range; external voltage 0.5V–1V sets proportional range - enables dynamic range optimization per signal level. |
| VCM | 1.5V common-mode bias | Provides stable DC bias for differential drivers; requires ≥2.2µF ceramic bypass to ground near pin to suppress switching noise and maintain INL. |
| D0–D11 | Parallel digital outputs | 12-bit MSB-first LVCMOS outputs; driven by separate OVDD (0.5V–3.6V) to interface directly with FPGAs, ASICs, or memory controllers without level shifters. |
| OF | Over/underflow flag | Active-high pulse indicates input exceeded selected full-scale range - used for automatic gain control (AGC) loop feedback in receiver chains. |
Key Features
| Feature | Design Value |
|---|---|
| Flexible input range selection | Programmable ±0.5V to ±1V differential range via SENSE pin voltage - allows SNR/SFDR trade-off tuning without hardware change (e.g., ±1V for max SNR in low-interference ultrasound; ±0.5V for improved SFDR in crowded spectrum). |
| Integrated clock duty cycle stabilizer | Compensates for asymmetric clock waveforms without external circuitry - maintains full 70.6dB SNR even with 40%–60% duty cycle, simplifying clock generation in FPGA-based systems. |
| Low transition noise | 0.3LSBRMS - reduces quantization uncertainty in high-resolution measurements such as Doppler shift detection or phase-sensitive demodulation. |
| Separate output supply (OVDD) | 0.5V–3.6V configurable logic interface - enables direct connection to 1.8V, 2.5V, or 3.3V FPGA I/O banks without level-shifting components or timing skew. |
| Multi-mode power management | Three operational states: full-speed (211mW), nap (15mW), shutdown (2mW) - supports battery-powered portable instruments with adaptive sampling duty cycles. |
Applications
| Ultrasound Imaging | Spectral Analysis |
|---|---|
Use Scenario: Digitizing RF echo signals from piezoelectric transducers operating at 2–15MHz center frequencies with wide dynamic range requirements. IC Role / Device Role / Timing Role: High-speed ADC capturing baseband or IF samples for beamforming and envelope detection; 575MHz bandwidth preserves harmonic content for tissue characterization. Use Value: 70.6dB SNR enables detection of low-amplitude echoes from deep tissue; ±0.4LSB INL ensures accurate B-mode grayscale rendering without shading artifacts. |
Use Scenario: Real-time frequency-domain monitoring of industrial vibration spectra or RF spectrum occupancy in cognitive radio test equipment. IC Role / Device Role / Timing Role: Front-end digitizer feeding FFT engines; 90dB SFDR prevents false peaks from harmonic leakage during multi-tone analysis. Use Value: No missing codes and 0.3LSBRMS transition noise ensure precise amplitude calibration across 4096-point FFT bins; low power allows fanless embedded deployment. |
| Wireless Communication Receiver | Portable Instrumentation |
Use Scenario: Direct-conversion or low-IF receiver in LTE/WiMAX base station prototypes requiring wide instantaneous bandwidth and high spurious-free operation. IC Role / Device Role / Timing Role: Digitizing 20–40MHz IF signals with minimal phase noise contribution; clock duty cycle stabilizer tolerates FPGA-generated clocks with variable duty cycle. Use Value: 5-cycle pipeline latency enables deterministic timing for digital downconversion; separate OVDD supports 1.8V FPGA interfacing to reduce system power. |
Use Scenario: Handheld oscilloscope or signal analyzer where size, battery life, and measurement fidelity are jointly constrained. IC Role / Device Role / Timing Role: Core ADC in mixed-signal SoM; nap/shutdown modes extend battery runtime during idle periods without losing configuration state. Use Value: 211mW at 80Msps enables >4-hour operation on 2000mAh Li-ion; 32-pin QFN (5×5mm) minimizes PCB area versus older 48-pin TQFP alternatives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC2249CUH#PBF | 14-bit resolution, same 80Msps rate, 73.5dB SNR, 92dB SFDR, 240mW power - higher resolution but 29mW higher dissipation. | Better suited for applications requiring >12 ENOB (e.g., high-precision radar pulse analysis), less ideal where power or FPGA resource count is constrained. | Select LTC2249CUH#PBF when 14-bit linearity and 2.9dB SNR improvement justify added power and cost; retain LTC2229CUH#PBF for optimal 12-bit power/performance balance. |
| AD9229BCPZ-80 | Analog Devices 12-bit, 80Msps ADC; 70.2dB SNR, 88dB SFDR, 220mW; different pinout (32-pin LFCSP vs QFN), no integrated VCM or SENSE-based range control. | Requires external common-mode bias and reference scaling circuitry; lacks clock duty cycle stabilizer - demands cleaner clock sources. | Choose AD9229BCPZ-80 only if existing layout uses identical footprint and external reference design is already validated; LTC2229CUH#PBF offers superior integration for new designs. |
Compared with LTC2249CUH#PBF and AD9229BCPZ-80, the LTC2229CUH#PBF uniquely combines 12-bit precision with integrated VCM generation, SENSE-programmable input range, and clock duty cycle stabilization - reducing BOM count and layout complexity while maintaining best-in-class 70.6dB SNR at 211mW.
Availability
LTC2229CUH#PBF is available at Aetrix Electronics and suitable for ultrasound imaging systems, portable spectrum analyzers, and wireless communication receivers requiring stable component supply, long-term lifecycle support, and traceable sourcing for medical and industrial certifications.
Supply support for LTC2229CUH#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC2229CUH#PBF belongs to Linear's high-speed ADC product line, designed specifically for demanding digitization tasks in medical imaging, test equipment, and broadband communications where AC performance, power efficiency, and integration density are critical.
FAQ
What is the operating temperature range for the LTC2229CUH#PBF?
The LTC2229CUH#PBF is rated for commercial temperature operation from 0°C to 70°C. This grade is specified in the part number suffix "C" (as in CUH), distinguishing it from the industrial-grade LTC2229IUH#PBF (–40°C to 85°C). All DC and AC specifications in the datasheet marked with ● apply across this full 0°C–70°C range.
Does the LTC2229CUH#PBF require an external reference voltage?
No, the LTC2229CUH#PBF includes an internal 1.5V bandgap reference and differential reference buffer. It supports fully self-contained operation using the SENSE pin to select ±0.5V or ±1V input range. External references are optional and only needed when custom input ranges between 0.5V and 1V are required via resistor divider on SENSE.
How does the MODE pin affect output data format and clock functionality in the LTC2229CUH#PBF?
The MODE pin on the LTC2229CUH#PBF selects both output coding and clock duty cycle stabilizer (DCS) state. Ground = offset binary + DCS disabled; 1/3VDD = offset binary + DCS enabled; 2/3VDD = 2's complement + DCS enabled; VDD = 2's complement + DCS disabled. DCS improves SNR when CLK duty cycle deviates from 50%.
Can the LTC2229CUH#PBF interface directly with a 1.8V FPGA I/O bank?
Yes, the LTC2229CUH#PBF supports direct interfacing with 1.8V logic through its dedicated OVDD supply pin (Pin 21). When OVDD = 1.8V, VOH is guaranteed ≥1.79V and VOL ≤0.09V under 1.6mA load - meeting standard 1.8V LVCMOS input thresholds without level shifters or pull-up resistors.
What is the purpose of the OF (Over/Under Flow) pin on the LTC2229CUH#PBF?
The OF pin on the LTC2229CUH#PBF is an active-high flag that pulses high whenever the analog input exceeds the selected full-scale range (±0.5V or ±1V), indicating clipping or saturation. It is used in real-time AGC loops to dynamically adjust front-end gain and prevent data corruption in receiver chains.
LTC2229CUH#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.4V
- Voltage - Supply, Digital:
- 2.7V ~ 3.4V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 32-QFN (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2229CUH#PBF FAQ
1.How can I place an order for LTC2229CUH#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2229CUH#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2229CUH#PBF reliable?
The price and inventory of LTC2229CUH#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2229CUH#PBF is usually 5 days.
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Once your LTC2229CUH#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2229CUH#PBF?
For technical support, including LTC2229CUH#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2229CUH#PBF requirements.
6.How does Aetrix verify that LTC2229CUH#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2229CUH#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2229CUH#PBF meets industry standards.
7.What is the process for return or replacement of LTC2229CUH#PBF?
All LTC2229CUH#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2229CUH#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2229CUH#PBF part is unused and in its original packaging.
Return procedure for LTC2229CUH#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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