Analog Devices Inc. LTC2260CUJ-12#PBF

Overview

LTC2260CUJ-12#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 105 Msps ultralow-power analog-to-digital converter with 70.4 dB SNR and 85 dB SFDR at 70 MHz input. It operates from a single 1.8 V supply, supports CMOS/DDR CMOS/DDR LVDS outputs, and features 800 MHz full-power bandwidth for undersampling RF/IF signals in communications systems.

For engineers reviewing the LTC2260CUJ-12#PBF datasheet, LTC2260CUJ-12#PBF pinout, LTC2260CUJ-12#PBF application, or LTC2260CUJ-12#PBF equivalent, key selection criteria include sampling rate (105 Msps), power dissipation (103 mW at sine-wave input), differential input range (1–2 V_P-P), and QFN-40 package compatibility with pin-compatible 12-/14-bit family members.

Technical Context

The LTC2260CUJ-12#PBF implements a 12-bit pipelined ADC architecture with integrated sample-and-hold, correction logic, and configurable digital output drivers. Its 0.17 ps_RMS aperture jitter enables high-fidelity undersampling of IF frequencies up to 140 MHz while maintaining 70.4 dB SNR performance.

Dual reference modes-internal (±1 V or ±0.5 V via SENSE pin) or external (0.625–1.3 V)-support flexible input scaling. Clock interface accepts differential (ENC+/ENC−) or single-ended inputs, with optional duty cycle stabilizer enabling robust operation across wide clock duty cycles without external conditioning.

Key Specifications

Pinout & Package

40-pin (6 mm × 6 mm) plastic QFN package with exposed thermal pad (Pin 41 = GND). Pinout varies by digital output mode (full-rate CMOS, DDR CMOS, or DDR LVDS); all variants share identical analog, clock, and control pin assignments.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9226BSTZ-105, the LTC2260CUJ-12#PBF delivers 65% lower power and 1.8 V operation ideal for portable systems, while LTC2261CUJ-12#PBF offers seamless upgrade path to 125 Msps without layout or firmware redesign.

Availability

LTC2260CUJ-12#PBF is available at Aetrix Electronics and suitable for cellular base stations, software defined radios, and portable medical imaging requiring stable component supply across extended production lifecycles.

Supply support for LTC2260CUJ-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and DSP technologies for precision signal processing.

The LTC2260CUJ-12#PBF belongs to the LTC22xx ultra-low-power, high-speed ADC product line designed specifically for demanding communications, instrumentation, and medical imaging applications where SNR, SFDR, and power efficiency are critical.

FAQ

What is the maximum sampling rate supported by the LTC2260CUJ-12#PBF?

The LTC2260CUJ-12#PBF is rated for a maximum sampling rate of 105 Msps, as specified in its part number suffix "-12" and confirmed in the Absolute Maximum Ratings and Dynamic Accuracy tables. This rate is fixed for the LTC2260-12 variant and cannot be increased beyond 105 Msps even with optimized clocking or reduced resolution settings. The LTC2260CUJ-12#PBF maintains full 12-bit performance-including 70.4 dB SNR and 85 dB SFDR-at this rate.

Does the LTC2260CUJ-12#PBF support both internal and external voltage references?

Yes, the LTC2260CUJ-12#PBF supports both internal and external reference configurations via the SENSE pin (Pin 39). Tying SENSE to VDD selects the internal ±1 V range; tying it to GND selects ±0.5 V; applying 0.625–1.3 V externally configures ±0.8×V_SENSE. Internal reference accuracy is ±1.5% FS gain error and ±20 µV/°C offset drift, while external reference mode bypasses internal buffers for higher precision when using low-noise external sources.

What digital output interfaces does the LTC2260CUJ-12#PBF support?

The LTC2260CUJ-12#PBF supports three digital output interface modes: full-rate CMOS, double-data-rate (DDR) CMOS, and DDR LVDS. Mode selection is controlled by the SCK pin in parallel programming mode (PAR/SER = VDD) or via SPI register writes in serial mode. CMOS outputs operate from 1.2–1.8 V OVDD and drive standard FPGA I/O banks; DDR LVDS uses 100 Ω on-chip termination and 1.75/3.5 mA current modes for low-EMI, high-speed links.

Is the LTC2260CUJ-12#PBF pin-compatible with other devices in the LTC226x family?

Yes, the LTC2260CUJ-12#PBF is fully pin-compatible with the LTC2261CUJ-12#PBF and LTC2259CUJ-12#PBF in the 40-lead QFN (UJ) package. All share identical pin functions, power sequencing, and SPI register maps. This allows hardware reuse across 80/105/125 Msps variants and simplifies design scalability-only clock frequency and firmware configuration need adjustment when upgrading or downgrading sampling rate.

What power-saving modes are available on the LTC2260CUJ-12#PBF?

The LTC2260CUJ-12#PBF provides two low-power states: Nap mode (9 mW) and Sleep mode (0.5 mW). Nap mode retains register settings and reference bias while disabling the ADC core and output drivers; Sleep mode powers down nearly all circuitry except basic bias networks. Both are entered via SDI pin control in parallel mode or SPI command in serial mode, enabling rapid wake-up (<1 µs) for burst-mode acquisition in battery-powered test equipment and IoT edge sensors.