Analog Devices Inc. LTC2260IUJ-14#PBF

Overview

LTC2260IUJ-14#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, 105 Msps ultralow-power analog-to-digital converter optimized for undersampling high-frequency IF signals in communications infrastructure. It delivers 73.4 dB SNR, 85 dB SFDR, and 0.17 psRMS aperture jitter with single 1.8 V supply, CMOS/DDR CMOS/DDR LVDS outputs, and 800 MHz full-power bandwidth - enabling direct digitization of 70–140 MHz cellular and SDR waveforms.

For engineers reviewing the LTC2260IUJ-14#PBF datasheet, LTC2260IUJ-14#PBF pinout, LTC2260IUJ-14#PBF application, or LTC2260IUJ-14#PBF equivalent, key selection criteria include sampling rate compatibility (105 Msps), temperature grade (–40°C to +85°C), QFN-40 package thermal performance, and output mode configurability (CMOS vs. LVDS) for FPGA interface timing closure and power budgeting.

Technical Context

The LTC2260IUJ-14#PBF implements a 14-bit pipelined ADC architecture with integrated sample-and-hold, correction logic, and configurable digital output drivers. Its 0.17 psRMS jitter enables clean undersampling of 70–140 MHz IF inputs without external clock conditioning, while the optional duty cycle stabilizer maintains performance across wide input clock duty cycles (20%–80%).

It supports three digital output modes - full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS - each with independent OVDD supply (1.2–1.9 V for CMOS; 1.7–1.9 V for LVDS) and on-chip termination (100 Ω for LVDS). The SPI-configurable serial port (CS/SCK/SDI/SDO) and parallel control pins (ENC+/ENC–, PAR/SER) allow flexible system integration in real-time signal processing chains.

Key Specifications

Pinout & Package

40-lead (6 mm × 6 mm) plastic QFN package with exposed thermal pad (Pin 41 = GND), rated for –40°C to +85°C operation. Pinout varies by output mode (CMOS/LVDS); all configurations share common analog and control pins.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9246BCPZ-105, the LTC2260IUJ-14#PBF integrates reference and duty cycle stabilization, reducing BOM count and improving jitter margin; compared with LTC2261IUJ-14#PBF, it trades 20 Msps speed for 21 mW lower power and relaxed FPGA interface timing - ideal for thermally constrained portable designs.

Availability

LTC2260IUJ-14#PBF is available at Aetrix Electronics and suitable for cellular base stations, software defined radios, and portable medical imaging requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for LTC2260IUJ-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its high-performance signal chain portfolio, emphasizing precision, speed, and power efficiency for demanding analog applications.

The LTC2260IUJ-14#PBF belongs to the LTC226x family of ultralow-power, high-SFDR ADCs designed specifically for undersampling IF signals in wireless infrastructure, defense electronics, and portable instrumentation where thermal headroom and dynamic range are critical.

FAQ

What is the maximum input frequency supported by the LTC2260IUJ-14#PBF?

The LTC2260IUJ-14#PBF features an 800 MHz full-power bandwidth, allowing it to accurately digitize analog inputs up to 400 MHz in Nyquist zone 2. At 105 Msps sampling, this supports undersampling of 70–140 MHz IF signals commonly used in LTE and SDR applications, with measured SFDR >85 dB up to 140 MHz.

Does the LTC2260IUJ-14#PBF require an external reference voltage?

No - the LTC2260IUJ-14#PBF includes an internal 1.25 V reference with ±25 ppm/°C drift and supports external reference via the SENSE pin (0.625–1.3 V). When SENSE is tied to VDD, the device uses internal reference with ±1 V input range; grounding SENSE selects ±0.5 V range. External reference is optional and used only for enhanced DC accuracy.

How does the clock duty cycle stabilizer function in the LTC2260IUJ-14#PBF?

The LTC2260IUJ-14#PBF's clock duty cycle stabilizer corrects input clock asymmetry in real time, enabling full-performance operation with duty cycles from 20% to 80%. It is enabled by driving CS high in parallel programming mode and reduces aperture uncertainty caused by skewed clock edges - eliminating the need for external clock conditioners in systems using crystal oscillators or PLLs with poor duty cycle control.

What digital output formats does the LTC2260IUJ-14#PBF support?

The LTC2260IUJ-14#PBF supports three output formats: full-rate CMOS (14-bit parallel at 105 MHz), double-data-rate CMOS (7-bit nibbles at 210 MHz), and double-data-rate LVDS (7-bit differential pairs at 210 MHz). Output mode is selected via SCK in parallel mode or SPI register write; OVDD voltage (1.2–1.9 V for CMOS, 1.7–1.9 V for LVDS) sets swing and drive strength.

Is the LTC2260IUJ-14#PBF pin-compatible with other devices in the LTC226x family?

Yes - the LTC2260IUJ-14#PBF shares identical 40-pin QFN (6 mm × 6 mm) packaging, pinout, and footprint with LTC2261IUJ-14#PBF (125 Msps) and LTC2259IUJ-14#PBF (80 Msps). This enables scalable design reuse: upgrading sampling rate or optimizing for power requires only firmware and clock source changes - no PCB revision needed.