Analog Devices Inc. LTC2261CUJ-14#TRPBF

Overview

LTC2261CUJ-14#TRPBF from Analog Devices (formerly Linear Technology) is a 14-bit, 125Msps ultralow-power pipelined ADC with 73.4dB SNR, 85dB SFDR, and 0.17psRMS jitter. It operates from a single 1.8V supply, supports CMOS/DDR-CMOS/DDR-LVDS outputs, and targets high-frequency undersampling in cellular base stations and software-defined radios.

For engineers reviewing the LTC2261CUJ-14#TRPBF datasheet, LTC2261CUJ-14#TRPBF pinout, LTC2261CUJ-14#TRPBF application, or LTC2261CUJ-14#TRPBF equivalent, key selection criteria include full-power bandwidth (800MHz), input range configurability (1–2VP-P), optional clock duty cycle stabilizer, serial SPI configuration interface, and QFN-40 thermal performance (θJA = 32°C/W).

Technical Context

The LTC2261CUJ-14#TRPBF implements a 14-bit pipeline ADC architecture with integrated sample-and-hold, correction logic, and configurable digital output drivers. Its analog front-end supports differential sine-wave, PECL, LVDS, TTL, or CMOS encode inputs and offers selectable internal/external reference modes via the SENSE pin.

Digital interface flexibility includes serial SPI for full register control (PAR/SER = GND) or parallel logic mode (PAR/SER = VDD) enabling sleep mode, clock duty cycle stabilization, and output format selection. Output voltage swing is programmable (1.2–1.8V for CMOS; 1.75/3.5mA for LVDS), and pipeline latency is fixed at 5.0 cycles (full-rate) or 5.5 cycles (DDR).

Key Specifications

Pinout & Package

Package: 40-lead (6mm × 6mm) plastic QFN (UJ package) with exposed thermal pad (Pin 41 = GND, must be soldered to PCB). θJA = 32°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9246BCPZ-125 and LTC2260CUJ-14#TRPBF, the LTC2261CUJ-14#TRPBF uniquely integrates a clock duty cycle stabilizer and supports seamless 1.2–1.8V CMOS output swing control - reducing BOM count and layout sensitivity in thermally tight RF subsystems.

Availability

LTC2261CUJ-14#TRPBF is available at Aetrix Electronics and suitable for cellular infrastructure, portable medical imaging, and multi-channel data acquisition requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LTC2261CUJ-14#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and RF ICs, serving precision instrumentation, communications, and industrial markets.

The LTC2261CUJ-14#TRPBF belongs to Linear's ultralow-power, high-speed ADC product line designed specifically for undersampling architectures in wireless infrastructure, defense electronics, and portable diagnostic equipment.

FAQ

What is the maximum sampling rate supported by the LTC2261CUJ-14#TRPBF?

The LTC2261CUJ-14#TRPBF supports a maximum sampling rate of 125Msps. This rating is specified under recommended operating conditions (VDD = OVDD = 1.8V, differential encode input, 2VP-P input range) and is validated across the commercial temperature range (0°C to 70°C). Performance metrics including SNR and SFDR are guaranteed at this rate.

Does the LTC2261CUJ-14#TRPBF support both internal and external voltage references?

Yes, the LTC2261CUJ-14#TRPBF supports both internal and external references. The SENSE pin selects between internal reference modes (±1V or ±0.5V input range), while applying 0.625–1.3V to SENSE enables external reference operation. Internal reference output (VREF = 1.25V ±25ppm/°C) and common-mode bias (VCM ≈ VDD/2) are provided on dedicated pins.

How does the clock duty cycle stabilizer function in the LTC2261CUJ-14#TRPBF?

The clock duty cycle stabilizer in the LTC2261CUJ-14#TRPBF corrects asymmetric encode clock waveforms to maintain optimal sampling aperture timing. Enabled via CS pin in parallel programming mode, it allows high AC performance even with duty cycles as low as 2.0ns high/low time - eliminating need for external clock conditioning circuits.

What digital output interface options are available on the LTC2261CUJ-14#TRPBF?

The LTC2261CUJ-14#TRPBF supports three digital output modes: full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS. Mode selection is controlled by PAR/SER and SCK pins. CMOS outputs support 1.2–1.8V swing (via OVDD); LVDS outputs provide 1.75mA or 3.5mA current drive with on-chip 100Ω termination.

Is the LTC2261CUJ-14#TRPBF pin-compatible with other devices in the LTC226x family?

Yes, the LTC2261CUJ-14#TRPBF is pin-compatible with the LTC2260-14 and LTC2259-14, sharing identical 40-pin QFN (6mm × 6mm) packaging, pin functions, and PCB footprint. This enables hardware scalability across 125Msps, 105Msps, and 80Msps sampling rates without layout revision.