Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Analog Devices Inc. LTC2265CUJ-12#PBF

Name: LTC2265CUJ-12#PBF
Brand: Analog Devices Inc.
SKU: LTC2265CUJ-12#PBF
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: LTC2265CUJ-12#PBF

Manufacturer:: Analog Devices Inc.

Category:: Analog to Digital Converters (ADC)

Package:: 40-WFQFN Exposed Pad

Datasheet:: LTC2265CUJ-12#PBF.pdf

Description:: IC ADC 12BIT PIPELINED 40QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,623

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

LTC2265CUJ-12#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, dual-channel, simultaneous-sampling analog-to-digital converter with 65 Msps maximum sampling rate, 71 dB SNR, 90 dB SFDR, and ultralow 0.15 ps_RMS aperture jitter - designed for high-fidelity IF digitization in communications infrastructure.

For engineers reviewing the LTC2265CUJ-12#PBF datasheet, LTC2265CUJ-12#PBF pinout, LTC2265CUJ-12#PBF application, or LTC2265CUJ-12#PBF equivalent, this page delivers verified specs, QFN-40 package mapping, LVDS serialization modes, input range configuration, and real-world trade-offs versus pin-compatible 14-bit and lower-speed variants.

Technical Context

The LTC2265CUJ-12#PBF integrates two independent 12-bit ADC cores sharing a single PLL-based clock path, supporting differential analog inputs up to 800 MHz full-power bandwidth and configurable 1VP-P to 2VP-P input ranges via SENSE pin voltage selection. It employs a serial LVDS output architecture with selectable 1-lane or 2-lane mode per channel.

Its internal clock duty cycle stabilizer enables robust operation across wide encode duty cycles, while SPI-configurable registers control serialization format, output current (1.75 mA or 3.5 mA), termination enable, and power modes (Nap: 60 mW, Sleep: 1 mW). The device operates from a single 1.8 V supply with total power dissipation of 167 mW at 65 Msps in 2-lane mode.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	12-bit, no missing codes over temperature - guarantees monotonicity and full code coverage in demanding acquisition systems.
Sampling Rate	65 Msps maximum - supports Nyquist sampling of signals up to 32.5 MHz or undersampling of IF bands up to 70 MHz with preserved SNR.
SNR / SFDR	71 dB SNR and 90 dB SFDR at 70 MHz input - enables high dynamic range signal capture in cellular base station receivers and SDR front ends.
Aperture Jitter	0.15 ps_RMS - limits sampling uncertainty to <0.01° phase error at 100 MHz, critical for wideband IF sampling integrity.
Power Consumption	167 mW total at 65 Msps (2-lane, 3.5 mA mode) - achieves high performance with sub-200 mW power budget for thermally constrained RF modules.
Analog Supply	Single 1.8 V (1.7 V–1.9 V) - simplifies power delivery and reduces board-level DC/DC count in compact wireless designs.
Output Interface	LVDS serial (1- or 2-lane per channel) with internal 100 Ω termination - minimizes PCB routing complexity and EMI vs parallel CMOS outputs.

Pinout & Package

Package: 40-lead (6 mm × 6 mm) plastic QFN (UJ), exposed pad (Pin 41) soldered to PCB ground for thermal and electrical integrity.

Pin/Terminal	Circuit Role	Design Meaning
AIN1+, AIN1–	Channel 1 differential analog input	Accepts 1VP-P to 2VP-P differential signal; common-mode bias provided by VCM1.
AIN2+, AIN2–	Channel 2 differential analog input	Independent sampling path; matched gain/offset with Channel 1 for coherent dual-channel operation.
ENC+, ENC–	Differential encode clock input	Triggers simultaneous sampling on both channels; supports sine, PECL, LVDS, TTL, or CMOS drive.
OUT1A+/–, OUT1B+/–	Channel 1 LVDS serialized data outputs	Deliver 12-/14-/16-bit data in 1- or 2-lane mode; configurable output current and internal termination.
OUT2A+/–, OUT2B+/–	Channel 2 LVDS serialized data outputs	Independent serialization path; timing-aligned with Channel 1 for time-interleaved or I/Q applications.
PAR/SER	Programming mode select	Ground = serial SPI control; VDD = parallel logic control (CS/SCK/SDI/SDO repurposed).
SENSE	Reference and input range programming	Voltage level sets internal reference mode and ±0.5 V / ±1 V / external reference input range.
VDD, OVDD, GND, OGND	Analog/digital supply and ground planes	Separate analog (VDD/GND) and output driver (OVDD/OGND) supplies minimize noise coupling into sensitive ADC core.

Key Features

Feature	Design Value
Simultaneous dual-channel sampling	Enables true I/Q demodulation or time-coherent multi-antenna capture without inter-channel skew.
Configurable LVDS serialization (1/2-lane)	Reduces interface pin count to 8–16 LVDS pairs vs 24+ CMOS lines, easing high-speed PCB layout and density constraints.
Internal clock duty cycle stabilizer	Allows use of asymmetric clocks (e.g., from FPGA PLLs) without SNR degradation - eliminates need for external duty-cycle correction.
Three low-power operating modes	Full operation (167 mW), Nap (60 mW), Sleep (1 mW) - supports dynamic power scaling in battery-backed or burst-mode systems.
Pin compatibility with LTC2264/LTC2263 families	Same 40-pin QFN footprint and pinout across 65/40/25 Msps variants - enables scalable design reuse and BOM rationalization.

Applications

Cellular Base Station Receiver	Software Defined Radio (SDR) Front End
Use Scenario: Digitizing 70 MHz IF signals from quadrature downconverters in LTE/FDD-TDD macrocell transceivers. IC Role / Device Role / Timing Role: Dual-channel ADC captures I and Q paths simultaneously with matched gain/offset and sub-0.15 ps jitter to preserve EVM and ACLR. Use Value: 90 dB SFDR rejects adjacent channel interference; 71 dB SNR supports 16-QAM/64-QAM demodulation at –1 dBFS input.	Use Scenario: Wideband spectrum sensing and agile waveform digitization in military/commercial SDR platforms. IC Role / Device Role / Timing Role: High-speed dual ADC provides reconfigurable sampling (25–65 Msps) and programmable input range for multi-standard operation. Use Value: 800 MHz input bandwidth enables direct sampling of L/S-band signals; LVDS serialization eases FPGA interface at >1 Gbps aggregate data rate.
Portable Medical Ultrasound Beamformer	Multichannel Data Acquisition System
Use Scenario: Time-of-flight echo digitization across 16–64 receive channels in handheld ultrasound probes. IC Role / Device Role / Timing Role: Two synchronized 12-bit channels per LTC2265CUJ-12#PBF digitize paired transducer elements with deterministic latency (6 cycles). Use Value: Low 167 mW power enables high channel density without thermal throttling; 0.3 LSB_RMS transition noise preserves image contrast resolution.	Use Scenario: High-precision vibration, acoustic emission, or strain monitoring in industrial predictive maintenance sensors. IC Role / Device Role / Timing Role: Simultaneous sampling across multiple sensor pairs ensures phase-coherent time-domain analysis for FFT-based diagnostics. Use Value: ±0.3 LSB INL and ±0.1 LSB DNL ensure accurate amplitude linearity; shutdown mode reduces idle power to 1 mW per device.

Cellular Base Station Receiver

Software Defined Radio (SDR) Front End

Use Scenario: Digitizing 70 MHz IF signals from quadrature downconverters in LTE/FDD-TDD macrocell transceivers.

IC Role / Device Role / Timing Role: Dual-channel ADC captures I and Q paths simultaneously with matched gain/offset and sub-0.15 ps jitter to preserve EVM and ACLR.

Use Value: 90 dB SFDR rejects adjacent channel interference; 71 dB SNR supports 16-QAM/64-QAM demodulation at –1 dBFS input.

Use Scenario: Wideband spectrum sensing and agile waveform digitization in military/commercial SDR platforms.

IC Role / Device Role / Timing Role: High-speed dual ADC provides reconfigurable sampling (25–65 Msps) and programmable input range for multi-standard operation.

Use Value: 800 MHz input bandwidth enables direct sampling of L/S-band signals; LVDS serialization eases FPGA interface at >1 Gbps aggregate data rate.

Portable Medical Ultrasound Beamformer

Multichannel Data Acquisition System

Use Scenario: Time-of-flight echo digitization across 16–64 receive channels in handheld ultrasound probes.

IC Role / Device Role / Timing Role: Two synchronized 12-bit channels per LTC2265CUJ-12#PBF digitize paired transducer elements with deterministic latency (6 cycles).

Use Value: Low 167 mW power enables high channel density without thermal throttling; 0.3 LSB_RMS transition noise preserves image contrast resolution.

Use Scenario: High-precision vibration, acoustic emission, or strain monitoring in industrial predictive maintenance sensors.

IC Role / Device Role / Timing Role: Simultaneous sampling across multiple sensor pairs ensures phase-coherent time-domain analysis for FFT-based diagnostics.

Use Value: ±0.3 LSB INL and ±0.1 LSB DNL ensure accurate amplitude linearity; shutdown mode reduces idle power to 1 mW per device.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, low-power ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
LTC2264CUJ-12#PBF	40 Msps max sampling rate; identical 40-pin QFN package, pinout, and feature set - lower power (112 mW) but reduced Nyquist bandwidth.	Suitable for sub-20 MHz IF or baseband sampling where 65 Msps is unnecessary; retains same software register map and LVDS interface.	Select when system bandwidth requirement is ≤20 MHz and lower power or cost is prioritized over speed headroom.
ADS52J90IRGCT	Texas Instruments 10-bit, 100 Msps dual ADC in 64-pin QFN; higher speed but lower resolution and no internal reference - requires external REF and clock conditioning.	Better suited for wideband radar or high-sample-rate oscilloscope front ends where 10-bit resolution suffices and external clocking is acceptable.	Choose only if ≥100 Msps is mandatory and 12-bit ENOB can be sacrificed; not pin- or register-compatible.

Compared with LTC2264CUJ-12#PBF, the LTC2265CUJ-12#PBF delivers +25 Msps speed and +55 mW power for wider IF capture; versus ADS52J90IRGCT, it trades 2 bits of resolution for integrated reference, lower jitter, and simpler power/signal chain - favoring communications-grade fidelity over raw sample rate.

Availability

LTC2265CUJ-12#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, portable medical imaging, software-defined radio, and multichannel test equipment requiring stable component supply and long-term production continuity.

Supply support for LTC2265CUJ-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.

The LTC2265CUJ-12#PBF belongs to the LTC226x family of low-power, high-SFDR dual ADCs engineered for communications, instrumentation, and medical imaging systems demanding simultaneous sampling, low jitter, and minimal power per channel.

FAQ

What is the maximum sampling rate supported by the LTC2265CUJ-12#PBF?

The LTC2265CUJ-12#PBF supports a maximum sampling rate of 65 Msps. This is its designated speed grade within the LTC226x family - distinct from the 40 Msps LTC2264-12 and 25 Msps LTC2263-12 variants. Performance specifications including SNR, SFDR, and power consumption are guaranteed at this rate under specified conditions (1.8 V supply, 2-lane LVDS mode, differential encode input).

Does the LTC2265CUJ-12#PBF require an external reference voltage?

No, the LTC2265CUJ-12#PBF includes an internal reference and supports three configurations via the SENSE pin: connecting SENSE to VDD selects ±1 V input range with internal reference; grounding SENSE selects ±0.5 V range; applying 0.625 V–1.3 V to SENSE enables external reference mode. VREF pin outputs a nominally 1.25 V buffered reference for external circuitry.

How many LVDS data lanes does the LTC2265CUJ-12#PBF use per channel?

The LTC2265CUJ-12#PBF supports both 1-lane and 2-lane LVDS serialization per channel, selected via the CS pin in parallel programming mode (PAR/SER = VDD). In 2-lane mode, each channel outputs two bits per clock edge (e.g., 12-bit word serialized over 6 cycles); in 1-lane mode, one bit per edge (12 cycles). Both modes maintain frame synchronization via FR+/FR–.

What power-saving modes are available on the LTC2265CUJ-12#PBF?

The LTC2265CUJ-12#PBF offers three power states: full operation (167 mW at 65 Msps), Nap mode (60 mW - clock active but ADC core idled), and Sleep mode (1 mW - all circuitry disabled except wake-up logic). These are controlled via SPI register writes or parallel logic inputs (SDI in PAR/SER = VDD mode), enabling dynamic power scaling in battery-powered or thermally constrained systems.

Is the LTC2265CUJ-12#PBF pin-compatible with other devices in the LTC226x family?

Yes, the LTC2265CUJ-12#PBF shares identical 40-pin QFN (UJ) package dimensions, pin assignment, and mechanical footprint with LTC2264-12 and LTC2263-12 variants. This allows direct PCB footprint reuse across speed grades - simplifying design iteration, prototyping, and BOM consolidation without layout changes.

LTC2265CUJ-12#PBF Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 40-WFQFN Exposed Pad

Packaging:: Tube

Product Status:: Active

Number of Bits:: 12

Sampling Rate (Per Second):: 65M

Number of Inputs:: 2

Input Type:: Differential

Data Interface:: LVDS - Serial

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 2

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 1.7V ~ 1.9V

Voltage - Supply, Digital:: 1.7V ~ 1.9V

Features:: Simultaneous Sampling

Operating Temperature:: 0°C ~ 70°C

Supplier Device Package:: 40-QFN (6x6)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

LTC2265CUJ-12#PBF FAQ

1.How can I place an order for LTC2265CUJ-12#PBF through Aetrix?

Please submit a Request for Quotation (RFQ) for LTC2265CUJ-12#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LTC2265CUJ-12#PBF reliable?

The price and inventory of LTC2265CUJ-12#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2265CUJ-12#PBF is usually 5 days.

3.What payment methods are accepted for LTC2265CUJ-12#PBF?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2265CUJ-12#PBF transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for LTC2265CUJ-12#PBF?

LTC2265CUJ-12#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LTC2265CUJ-12#PBF order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LTC2265CUJ-12#PBF?

For technical support, including LTC2265CUJ-12#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2265CUJ-12#PBF requirements.

6.How does Aetrix verify that LTC2265CUJ-12#PBF is sourced from the original manufacturer or authorized distributors?

All LTC2265CUJ-12#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2265CUJ-12#PBF meets industry standards.

7.What is the process for return or replacement of LTC2265CUJ-12#PBF?

All LTC2265CUJ-12#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2265CUJ-12#PBF, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LTC2265CUJ-12#PBF part is unused and in its original packaging.

Return procedure for LTC2265CUJ-12#PBF:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…