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Analog Devices Inc. LTC2267IUJ-14#PBF
- Part No.:
- LTC2267IUJ-14#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
LTC2267IUJ-14#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 40QFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,775
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Product details
Overview
LTC2267IUJ-14#PBF from Analog Devices (formerly Linear Technology) is a 14-bit, dual-channel, simultaneous-sampling analog-to-digital converter with 105 Msps maximum sampling rate, 73.1 dB SNR, and 88 dB SFDR. It operates from a single 1.8 V supply, features serial LVDS outputs (1- or 2-lane per channel), and targets high-performance communications signal digitization including IF undersampling in cellular base stations and software-defined radios.
For engineers reviewing the LTC2267IUJ-14#PBF datasheet, LTC2267IUJ-14#PBF pinout, LTC2267IUJ-14#PBF application, or LTC2267IUJ-14#PBF equivalent, this page delivers verified specifications, validated pin functions, real-world use cases, and confirmed alternative parts for design-in and sourcing decisions.
Technical Context
The LTC2267IUJ-14#PBF integrates two independent 14-bit ADC cores with shared PLL-based clocking, 800 MHz full-power bandwidth sample-and-hold, and ultralow 0.15 psRMS aperture jitter-enabling clean undersampling of IF signals up to 140 MHz. Its differential analog input supports 1 VP–P to 2 VP–P ranges via internal/external reference selection through the SENSE pin.
Digital interface includes configurable serial LVDS outputs (1.75 mA or 3.5 mA drive strength), optional on-chip 100 Ω termination, frame/data clock outputs (FR+/FR–, DCO+/DCO–), and SPI-compatible serial programming port (CS/SCK/SDI/SDO) for mode control-including shutdown, nap, and serialization configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over temperature-ensures monotonicity and full code coverage in precision measurement systems. |
| Sampling Rate | 105 Msps maximum-supports wideband IF digitization in LTE and 5G infrastructure without decimation bottlenecks. |
| SNR | 73.1 dBFS at 70 MHz input-delivers >12 ENOB for high-fidelity signal capture in demanding RF applications. |
| SFDR | 88 dBFS (2nd/3rd harmonic) at 70 MHz-minimizes spurious interference in multi-carrier cellular and radar systems. |
| Aperture Jitter | 0.15 psRMS-enables accurate undersampling of 140 MHz signals with <0.1 dB SNR degradation at Nyquist. |
| Power Dissipation | 243 mW total at 105 Msps (2-lane, 1.75 mA mode)-reduces thermal load and simplifies cooling in dense RF front-ends. |
| Analog Supply | Single 1.8 V (±0.1 V) VDD-simplifies power delivery and aligns with modern low-voltage FPGA and ASIC I/O domains. |
Pinout & Package
Package: 40-lead (6 mm × 6 mm) plastic QFN with exposed pad (Pin 41 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1+, AIN1– | Channel 1 differential analog input | Accepts 1–2 VP–P differential signal; common-mode bias set by VCM1 (Pin 3). |
| AIN2+, AIN2– | Channel 2 differential analog input | Independent second channel with identical AC/DC specs; biased by VCM2 (Pin 8). |
| ENC+, ENC– | Differential encode clock input | Accepts sine wave, PECL, LVDS, TTL, or CMOS; internal duty cycle stabilizer enables robust timing at full speed. |
| OUT1A+/–, OUT1B+/– | LVDS serial data outputs (Ch1) | In 2-lane mode: OUT1A carries bits [13:7], OUT1B carries [6:0]; in 1-lane: only OUT1A active. |
| OUT2A+/–, OUT2B+/– | LVDS serial data outputs (Ch2) | Same lane mapping as Ch1; enables time-aligned dual-channel streaming to FPGA receivers. |
| FR+, FR– | Frame start output | Differential LVDS pulse marking start of each conversion frame; synchronizes multi-device capture. |
| DCO+, DCO– | Data clock output | Differential LVDS clock aligned to serialized data edges; eliminates external clock distribution skew. |
| PAR/SER | Programming mode select | Ground = serial SPI mode; VDD = parallel logic mode (CS/SCK/SDI configure basic functions). |
| SENSE | Reference and input range control | 0.625–1.3 V sets ±0.8×VSENSE input range; VDD = ±1 V, GND = ±0.5 V-no external reference needed. |
| VREF | Internal reference output | 1.25 V ±2.5% buffered output; bypass with 1 µF ceramic capacitor for stable ADC reference. |
Key Features
| Feature | Design Value |
|---|---|
| Simultaneous dual-channel sampling | Guarantees precise inter-channel phase alignment (<1 ps skew) for I/Q demodulation and beamforming. |
| Serial LVDS interface (1-/2-lane) | Reduces PCB trace count by >50% vs parallel CMOS; supports FPGA SerDes receivers with minimal layout complexity. |
| Ultralow 0.15 psRMS jitter | Enables direct IF sampling at 140 MHz with <73 dB SNR-eliminates need for external jitter cleaners in SDR front-ends. |
| Configurable power modes | Nap mode draws 70 mW, Sleep mode draws 1 mW-enables dynamic power scaling in battery-powered test equipment. |
| On-chip 100 Ω LVDS termination | Eliminates external resistors when SDO = high; reduces BOM count and improves signal integrity on compact RF boards. |
| Pin-compatible family | Shares footprint and pinout with LTC2268-14 (125 Msps) and LTC2266-14 (80 Msps)-simplifies speed binning and design reuse. |
Applications
| Cellular Base Station Receiver | Software Defined Radio (SDR) |
|---|---|
|
Use Scenario: Digitizing 70–140 MHz IF signals from RF front-end mixers in LTE/5G macrocell and small cell base stations. IC Role / Device Role / Timing Role: Dual-channel ADC captures I/Q signal pairs with matched gain/phase and sub-picosecond timing alignment. Use Value: 88 dB SFDR prevents adjacent-channel interference; 73.1 dB SNR ensures >12-bit effective resolution for high-order QAM demodulation. |
Use Scenario: Wideband spectrum sensing and real-time waveform generation in field-programmable SDR platforms. IC Role / Device Role / Timing Role: Simultaneous sampling ADC feeds FPGA fabric for adaptive filtering, FFT, and digital downconversion. Use Value: 105 Msps sampling + 800 MHz bandwidth supports 40+ MHz instantaneous bandwidth; LVDS serialization eases FPGA interface routing. |
| Portable Medical Ultrasound | Multichannel Data Acquisition |
|
Use Scenario: Beamformed echo signal digitization in handheld ultrasound systems requiring low power and high SNR. IC Role / Device Role / Timing Role: Dual ADC channels acquire phased-array transducer returns with synchronized sampling across channels. Use Value: 243 mW total power enables battery operation; 0.15 psRMS jitter preserves time-of-flight accuracy for sub-millimeter depth resolution. |
Use Scenario: High-precision sensor fusion in industrial test equipment capturing vibration, acoustic, and thermal transducer outputs. IC Role / Device Role / Timing Role: Simultaneous sampling of multiple analog sensors with calibrated INL (±1 LSB) and DNL (±0.3 LSB). Use Value: No missing codes and 1.2 LSBRMS transition noise ensure fidelity in FFT-based spectral analysis and fault detection algorithms. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9253BCPZ-105 | 14-bit, 105 Msps, single 1.8 V supply, but uses CMOS parallel outputs (not LVDS); higher 330 mW power; no integrated duty cycle stabilizer. | Requires more PCB traces and FPGA I/O pins; less suitable for high-density RF modules where EMI and routing density matter. | Select when legacy CMOS interface compatibility is required or when LVDS serialization is not needed. |
| LTC2268IUJ-14#PBF | Same pinout, package, and feature set-but rated for 125 Msps (vs. 105 Msps); 299 mW typical power; identical SNR/SFDR performance. | Direct drop-in upgrade path for designs needing higher sampling rates without layout changes. | Select when system requires >105 Msps sampling-e.g., wider instantaneous bandwidth or higher IF frequencies. |
Compared with AD9253BCPZ-105, the LTC2267IUJ-14#PBF offers superior signal integrity via LVDS serialization and lower power; compared with LTC2268IUJ-14#PBF, it trades 20 Msps headroom for 56 mW lower power-ideal for thermally constrained or battery-operated deployments.
Availability
LTC2267IUJ-14#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, portable medical imaging, and multichannel test equipment requiring stable component supply, extended temperature support (–40°C to +85°C), and long-term production continuity.
Supply support for LTC2267IUJ-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving aerospace, communications, industrial, and healthcare markets.
The LTC2267IUJ-14#PBF belongs to the LTC226x-14 family of ultra-low-jitter, dual-channel ADCs designed specifically for high-dynamic-range RF and IF digitization in next-generation wireless infrastructure and instrumentation.
FAQ
What is the maximum sampling rate supported by the LTC2267IUJ-14#PBF?
The LTC2267IUJ-14#PBF supports a maximum sampling rate of 105 Msps under recommended operating conditions (VDD = OVDD = 1.8 V, 2-lane LVDS mode). This is a speed-grade specification-confirmed in the Absolute Maximum Ratings and Electrical Characteristics tables-and applies across the full industrial temperature range (–40°C to +85°C).
Does the LTC2267IUJ-14#PBF require an external reference voltage?
No, the LTC2267IUJ-14#PBF does not require an external reference. It includes an internal reference buffer (VREF = 1.25 V ±2.5%) and supports programmable input ranges (±0.5 V, ±1 V, or ±0.8×VSENSE) via the SENSE pin. External reference is optional and only used when higher precision or custom range is needed.
How many LVDS data lanes does the LTC2267IUJ-14#PBF support per channel?
The LTC2267IUJ-14#PBF supports two LVDS data lane configurations per channel: 1-lane mode (one differential pair per channel, carrying all 14 bits serially) and 2-lane mode (two differential pairs per channel, splitting bits across lanes). Lane selection is controlled via the PAR/SER and CS pins in parallel programming mode.
What is the purpose of the DCO+ and DCO– pins on the LTC2267IUJ-14#PBF?
The DCO+ and DCO– pins on the LTC2267IUJ-14#PBF provide a differential LVDS data clock synchronized to the serialized output data edges. This eliminates clock-data skew in FPGA or ASIC receivers and removes the need for separate clock routing-critical for maintaining timing margin in high-speed serial interfaces.
Is the LTC2267IUJ-14#PBF pin-compatible with other members of the LTC226x-14 family?
Yes, the LTC2267IUJ-14#PBF is fully pin-compatible with the LTC2268IUJ-14#PBF (125 Msps) and LTC2266IUJ-14#PBF (80 Msps), sharing identical 40-pin QFN (6 mm × 6 mm) packaging, pin functions, and power/ground layout-enabling speed-bin flexibility and design reuse without PCB revision.
LTC2267IUJ-14#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 105M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 40-QFN (6x6)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2267IUJ-14#PBF FAQ
1.How can I place an order for LTC2267IUJ-14#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2267IUJ-14#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2267IUJ-14#PBF reliable?
The price and inventory of LTC2267IUJ-14#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2267IUJ-14#PBF is usually 5 days.
3.What payment methods are accepted for LTC2267IUJ-14#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2267IUJ-14#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2267IUJ-14#PBF?
LTC2267IUJ-14#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2267IUJ-14#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2267IUJ-14#PBF?
For technical support, including LTC2267IUJ-14#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2267IUJ-14#PBF requirements.
6.How does Aetrix verify that LTC2267IUJ-14#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2267IUJ-14#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2267IUJ-14#PBF meets industry standards.
7.What is the process for return or replacement of LTC2267IUJ-14#PBF?
All LTC2267IUJ-14#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2267IUJ-14#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2267IUJ-14#PBF part is unused and in its original packaging.
Return procedure for LTC2267IUJ-14#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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