Analog Devices Inc. LTC2273CUJ#PBF

Overview

LTC2273CUJ#PBF from Analog Devices (acquired Linear Technology) is a 16-bit, 80Msps high-speed serial-output analog-to-digital converter with JESD204 interface, 700MHz full-power bandwidth, ±4.5LSB INL, and 77.7dBFS noise floor. It digitizes wide dynamic range RF/IF signals in cellular base stations, spectrum analyzers, and ATE systems using a PGA front end and ultra-low 80fs RMS jitter sampling clock.

For engineers reviewing the LTC2273CUJ#PBF datasheet, LTC2273CUJ#PBF pinout, LTC2273CUJ#PBF application, or LTC2273CUJ#PBF equivalent, key selection criteria include JESD204 serial output compliance, 80Msps sample rate at 0°C to 70°C, 40-pin 6mm × 6mm QFN package, and differential analog input support for 1.5VP-P or 2.25VP-P ranges.

Technical Context

The LTC2273CUJ#PBF implements a 16-bit pipelined ADC core with integrated 8B/10B serializer and JESD204-compliant CML output drivers (CMLOUT+/–). Its sample-and-hold stage supports 700MHz input bandwidth and uses internal dither and clock duty cycle stabilization to maintain SFDR >90dBc at 140MHz input.

It features a programmable gain amplifier (PGA) front end selecting between 1.5VP-P and 2.25VP-P input ranges, dual-mode SYNC signaling (active-low SYNC+ and active-high SYNC–), and configurable sample rate via SRR0/SRR1 pins - all operating from a single 3.3V analog supply and 1.2V–3.3V output supply (OVDD).

Key Specifications

Pinout & Package

40-pin 6mm × 6mm plastic QFN (UJ package) with exposed thermal pad (Pin 41 = GND). Requires soldering exposed pad to PCB ground plane for thermal and electrical performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9269BCPZ-80 and LTC2272CUJ#PBF, the LTC2273CUJ#PBF uniquely balances JESD204 serial efficiency, 80Msps throughput, and 700MHz analog bandwidth - making it optimal for new RF system designs targeting FPGA-based signal processing with minimal board area.

Availability

LTC2273CUJ#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, test equipment, and medical imaging systems requiring stable component supply across extended production lifecycles.

Supply support for LTC2273CUJ#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving aerospace, communications, industrial, and healthcare markets.

The LTC2273CUJ#PBF belongs to ADI's high-speed data converter product line, designed specifically for demanding RF/IF digitization in wireless infrastructure, instrumentation, and defense electronics where JESD204 interoperability and wide analog bandwidth are essential.

FAQ

What is the maximum input frequency supported by the LTC2273CUJ#PBF?

The LTC2273CUJ#PBF supports a full-power analog input bandwidth of 700MHz, enabling direct sampling of IF signals up to this frequency. Performance metrics such as SFDR >90dBc are validated at 140MHz input, and usable undersampling extends into the GHz range thanks to ultra-low 80fs RMS jitter - confirmed in the datasheet's typical performance graphs (Figure G20).

Does the LTC2273CUJ#PBF require external reference voltage?

No, the LTC2273CUJ#PBF integrates an internal reference generator and does not require an external reference. The device uses an internal 1.25V common-mode bias and self-calibrating architecture; external references are neither supported nor necessary for standard operation per the datasheet's "INTERNAL ADC REFERENCE GENERATOR" block diagram and specifications table.

How is JESD204 lane synchronization achieved on the LTC2273CUJ#PBF?

JESD204 lane synchronization on the LTC2273CUJ#PBF is initiated by asserting SYNC+ (active-low) or SYNC– (active-high) for ≥2 sample clock cycles. This triggers transmission of K28.5 comma characters, followed by data frames aligned to the JESD204 subclass 0 protocol. Latency from SYNC activation to first comma is fixed at 3 pipeline cycles (LATSC), as specified in the Timing Characteristics table.

What are the supply voltage requirements for the LTC2273CUJ#PBF?

The LTC2273CUJ#PBF requires VDD = 3.3V (±3.5%) for the analog core and OVDD = 1.2V to 3.3V for the CML output drivers. OVDD must be ≥1.4V when using differential 100Ω termination or AC-coupled outputs. All supplies must be bypassed with 0.1μF ceramic capacitors per the Pin Functions section and layout guidelines in the datasheet.

Can the LTC2273CUJ#PBF operate at sample rates below 80Msps?

Yes, the LTC2273CUJ#PBF supports variable sample rates from 20Msps to 80Msps, selected via SRR0/SRR1 pins. At reduced rates (e.g., 40Msps), power dissipation scales down proportionally, and AC performance remains consistent - verified in Figure G22 (SNR/SFDR vs Sample Rate) and the Timing Characteristics table where fS min = 20MHz is explicitly specified.