Analog Devices Inc. LTC2273IUJ#PBF

Overview

LTC2273IUJ#PBF from Analog Devices (acquired Linear Technology) is a 16-bit, 80Msps high-speed serial-output analog-to-digital converter with JESD204 interface, 700MHz full-power bandwidth, ±4.5LSB INL, and 77.7dBFS noise floor. It digitizes wide dynamic range RF/IF signals in cellular base stations, spectrum analyzers, and ATE systems using a PGA front end and ultra-low 80fs RMS jitter sampling clock.

For engineers reviewing the LTC2273IUJ#PBF datasheet, LTC2273IUJ#PBF pinout, LTC2273IUJ#PBF application, or LTC2273IUJ#PBF equivalent, key selection criteria include JESD204 compliance, 80Msps sample rate at –40°C to +85°C, 1.5VP-P/2.25VP-P input range configurability, and 40-pin 6mm × 6mm QFN package thermal performance.

Technical Context

The LTC2273IUJ#PBF implements a 16-bit pipelined ADC core with integrated 8B/10B serializer and clock duty cycle stabilizer, supporting JEDEC JESD204A serial output at up to 1.6Gbps. Its sample-and-hold front end delivers 700MHz bandwidth and 100dB SFDR at low input frequencies.

Internal PGA enables two differential input ranges (1.5VP-P or 2.25VP-P), while configurable dither, scrambler, and pattern generation support test and synchronization functions. The device accepts differential or single-ended ENC+/ENC– clocks (PECL/LVDS/TTL/CMOS) and features SYNC+/SYNC– for JESD204 frame alignment.

Key Specifications

Pinout & Package

40-lead 6mm × 6mm plastic QFN (UJ package) with exposed thermal pad (Pin 41 = GND). Package meets industrial temperature range (–40°C to +85°C) and supports reflow soldering per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with AD9268BCPZ-80 and LTC2263IUP#PBF, the LTC2273IUJ#PBF offers superior SFDR at high input frequencies and native JESD204A compliance-critical for FPGA-based signal processing where lane count and deterministic latency matter.

Availability

LTC2273IUJ#PBF is available at Aetrix Electronics and suitable for cellular infrastructure, test equipment, and spectrum analysis applications requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LTC2273IUJ#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2273IUJ#PBF belongs to ADI's high-speed data converter product line, designed specifically for demanding RF/IF digitization in wireless infrastructure and instrumentation where JESD204 interface, wide bandwidth, and low jitter are essential.

FAQ

What is the operating temperature range for the LTC2273IUJ#PBF?

The LTC2273IUJ#PBF is rated for industrial operation from –40°C to +85°C. This range is validated across all key specifications including INL (±4.5LSB), DNL (±1LSB), SFDR (100dBc at 5MHz), and power dissipation (1100mW), ensuring reliability in base station and ATE environments.

Does the LTC2273IUJ#PBF support JESD204A or JESD204B?

The LTC2273IUJ#PBF implements the JESD204A standard, not JESD204B. It provides a single-lane, 16-bit serialized output at up to 1.6Gbps with K28.5 comma detection, SYNC+-initiated frame alignment, and deterministic pipeline latency of 9 clock cycles.

What input voltage ranges does the LTC2273IUJ#PBF support?

The LTC2273IUJ#PBF supports two differential analog input ranges: 1.5VP-P and 2.25VP-P, selected via the PGA pin. Both ranges maintain full 16-bit performance with 77.7dBFS noise floor and 100dB SFDR at low frequencies, enabling optimization for signal amplitude and SNR.

How is the LTC2273IUJ#PBF's clock input configured for single-ended operation?

For single-ended ENC clock input, drive ENC+ with a TTL/CMOS signal and bypass ENC– to GND with a 0.1μF capacitor. The internal 6.2kΩ bias on ENC– sets its common-mode voltage to 1.6V, allowing robust single-ended triggering while maintaining specified timing jitter and aperture delay.

What is the purpose of the exposed pad (Pin 41) on the LTC2273IUJ#PBF QFN package?

The exposed pad (Pin 41) on the LTC2273IUJ#PBF is electrically connected to GND and serves as the primary thermal path. It must be soldered to a PCB copper pour tied to the system ground plane to dissipate 1100mW and maintain junction temperature within limits across the –40°C to +85°C range.