Analog Devices Inc. LTC2289IUP#PBF
- Part No.:
- LTC2289IUP#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LTC2289IUP#PBF.pdf
- Description:
- IC ADC 10BIT PIPELINED 64QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2289IUP#PBF from Analog Devices (formerly Linear Technology) is a dual 10-bit, 80Msps low-noise 3V analog-to-digital converter designed for high-frequency signal digitization in demanding communications and imaging systems. It delivers 61.6dB SNR at 70MHz input, 85dB SFDR, and 110dB channel isolation, operating from a single 2.7V–3.4V supply with 422mW total power consumption.
For engineers reviewing the LTC2289IUP#PBF datasheet, LTC2289IUP#PBF pinout, LTC2289IUP#PBF application, or LTC2289IUP#PBF equivalent, key selection considerations include its dual-channel pipelined architecture, flexible 1VP-P to 2VP-P differential input range, clock duty cycle stabilizer, multiplexed or separate 10-bit parallel output buses, and –40°C to +85°C industrial temperature grade.
Technical Context
The LTC2289IUP#PBF implements a six-stage CMOS pipelined ADC architecture per channel, achieving 5-cycle pipeline latency and supporting simultaneous sampling of two independent analog inputs. Its integrated clock duty cycle stabilizer enables full-speed operation across wide input clock duty cycles (5%–95%), while internal 1.5V VCM bias generation and programmable reference scaling via SENSEA/SENSEB pins support ±0.5V to ±1V differential input ranges.
Each channel features independent shutdown (SHDNA/SHDNB), output enable (OEA/OEB), and overflow detection (OFA/OFB), with configurable output format (offset binary or 2's complement) via MODE pin. The device uses separate analog (VDD) and digital output (OVDD) supplies, allowing interface to 0.5V–3.6V logic families without level-shifting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 10-bit with no missing codes - guarantees monotonic transfer function and deterministic code mapping for precision measurement. |
| Sample Rate | 80Msps maximum - supports Nyquist bandwidth up to 40MHz and alias-free capture of signals beyond 140MHz via undersampling. |
| SNR @ 70MHz | 61.6dBFS - enables >10-bit effective resolution for RF and IF sampling in wireless infrastructure receivers. |
| SFDR @ 70MHz | 85dBc - suppresses spurious tones critical for spectral purity in baseband and intermediate frequency digitization. |
| Channel Isolation | –110dB at 100MHz - prevents crosstalk-induced distortion in time-interleaved or dual-path architectures. |
| Input Bandwidth | 575MHz full-power - accommodates wideband analog front-ends without external anti-alias filtering below ~200MHz. |
| Power Consumption | 422mW at 80Msps - balances performance and thermal budget for compact, convection-cooled instrumentation designs. |
Pinout & Package
Package: 64-lead (9mm × 9mm) plastic QFN with exposed GND pad (Pin 65), rated for –40°C to +85°C operation. Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AINA+, AINA– AINB+, AINB– |
Differential analog inputs (Ch A/B) | Accept ±0.5V to ±1V differential signals referenced to 1.5V common-mode; require matched 100Ω source impedance for optimal SFDR. |
| CLKA, CLKB | Single-ended sample clocks (Ch A/B) | Positive-edge triggered; support independent or synchronized sampling; duty cycle stabilizer reduces jitter sensitivity. |
| DA0–DA9, DB0–DB9 | 10-bit parallel digital outputs (Ch A/B) | Configurable as separate buses or multiplexed onto shared bus via MUX pin; output voltage swing set by OVDD (0.5V–3.6V). |
| OFA, OFB | Overflow/underflow flags (Ch A/B) | Active-high indication of input exceeding full-scale range - enables real-time clipping detection in FPGA-based signal processing pipelines. |
| SHDNA, SHDNB OEA, OEB |
Per-channel shutdown & output enable | Support independent power gating and tri-state control - allows dynamic channel disabling to reduce system power during idle periods. |
| MODE, MUX | Global configuration controls | MODE selects output format (offset binary/2's complement) and duty cycle stabilizer; MUX swaps output bus assignment between channels. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dual ADC cores | Two fully independent 10-bit 80Msps converters in one QFN package - eliminates inter-chip timing skew and reduces board area vs discrete solutions. |
| Flexible input range programming | ±0.5V to ±1V differential range selectable per channel via SENSEA/SENSEB pins - simplifies front-end design across varying signal chain gain stages. |
| On-chip 1.5V common-mode reference | VCMA/VCMB pins provide low-drift (±25ppm/°C), low-impedance (4Ω) 1.5V bias - eliminates need for external op-amp driver in transformer-coupled applications. |
| Low aperture jitter | 0.2psRMS - minimizes noise floor degradation when sampling high-frequency signals (e.g., 140MHz input yields SNR >61dBFS). |
| Multiple power management modes | Shutdown (2mW/channel), Nap (15mW/channel), and active (422mW total) - enables adaptive power scaling in battery-powered portable test equipment. |
Applications
| Wireless Base Station Receiver | Medical Ultrasound Beamformer |
|---|---|
|
Use Scenario: Digitizing 70–140MHz IF signals from quadrature demodulators in LTE/5G macrocell radios. IC Role / Device Role / Timing Role: Dual-channel ADC capturing I/Q data streams with <62dB SNR and <85dB SFDR to preserve EVM and ACLR specifications. Use Value: 110dB channel isolation prevents I/Q crosstalk that would degrade image rejection ratio and increase adjacent channel interference. |
Use Scenario: Sampling echo return signals from phased-array transducers operating at 5–15MHz center frequencies. IC Role / Device Role / Timing Role: High-speed dual ADC acquiring time-aligned RF beam samples for digital beamforming and harmonic suppression. Use Value: 575MHz input bandwidth supports direct sampling of fundamental and second-harmonic ultrasound bands without analog downconversion. |
| Spectral Analysis Instrumentation | Portable RF Test Equipment |
|
Use Scenario: Real-time FFT-based spectrum analysis in handheld analyzers requiring >80dB dynamic range over 100MHz span. IC Role / Device Role / Timing Role: Dual ADC feeding FPGA-based FFT engines with low transition noise (0.08LSBRMS) to minimize spectral leakage. Use Value: 61.6dB SNR at 70MHz ensures accurate amplitude measurement of weak signals buried beneath strong interferers in crowded RF environments. |
Use Scenario: Battery-powered field testers performing modulation analysis on cellular and Wi-Fi signals. IC Role / Device Role / Timing Role: Low-power dual ADC enabling 8-hour operation on Li-ion packs while maintaining 10-bit ENOB at 80Msps. Use Value: Shutdown mode (2mW/channel) and Nap mode (15mW/channel) extend runtime during idle intervals without compromising wake-up latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC2294IUP#PBF | 12-bit resolution, same 80Msps rate, higher 66.5dB SNR but 450mW power - requires tighter layout for analog isolation. | Better suited for high-fidelity IF sampling where 2-bit resolution gain justifies added power and cost. | Select LTC2294IUP#PBF when ENOB >11 bits is required and thermal headroom permits +30mW dissipation. |
| AD9233BCPZ-80 | Single-channel 12-bit 80Msps ADC from Analog Devices; no integrated duty cycle stabilizer or dual-channel isolation. | Requires two devices and precise clock/data alignment for dual-path systems - increases BOM count and layout complexity. | Choose AD9233BCPZ-80 only for space-constrained single-channel applications where dual-channel integration is unnecessary. |
Compared with LTC2294IUP#PBF and AD9233BCPZ-80, the LTC2289IUP#PBF uniquely delivers 10-bit dual-channel conversion with integrated clock stabilization, channel isolation, and flexible power modes in a single 9mm × 9mm QFN - reducing component count and layout risk in compact, multi-channel RF digitizers.
Availability
LTC2289IUP#PBF is available at Aetrix Electronics and suitable for wireless infrastructure, medical ultrasound, spectral analysis, and portable RF test equipment requiring stable component supply across extended temperature ranges.
Supply support for LTC2289IUP#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2289IUP#PBF belongs to ADI's high-speed precision ADC product line, engineered for wideband digitization in communications receivers, instrumentation, and medical imaging where low noise, high isolation, and dual-channel synchronization are critical.
FAQ
What is the operating temperature range for the LTC2289IUP#PBF?
The LTC2289IUP#PBF is specified for industrial operation from –40°C to +85°C, as indicated by the "I" grade suffix in the part number. This rating is validated across all AC and DC specifications including SNR, SFDR, INL, and DNL, making it suitable for deployment in outdoor base stations, factory-floor test gear, and mobile medical devices without derating.
Does the LTC2289IUP#PBF support single-ended analog inputs?
Yes, the LTC2289IUP#PBF supports single-ended drive: connect AIN+ to the signal and AIN– to the 1.5V VCM pin (VCMA or VCMB). However, harmonic distortion and INL degrade relative to differential operation, while SNR and DNL remain unaffected. For best performance, differential drive with matched 100Ω source impedance is strongly recommended.
How does the clock duty cycle stabilizer in the LTC2289IUP#PBF improve system performance?
The clock duty cycle stabilizer in the LTC2289IUP#PBF corrects input clock asymmetry to maintain consistent aperture timing, enabling full 80Msps performance even with input clocks having 5%–95% duty cycles. This eliminates the need for external clock conditioning circuits and improves SNR stability in systems using crystal oscillators or PLLs with variable duty cycle output.
Can the LTC2289IUP#PBF output buses be multiplexed onto a single 10-bit data path?
Yes, the LTC2289IUP#PBF supports multiplexed output via the MUX pin: when MUX = LOW, Channel A data appears on DB0–DB9/OFB and Channel B on DA0–DA9/OFA; when MUX = HIGH, the assignments reverse. This allows both channels to share one FPGA or ASIC data bus, reducing pin count and PCB routing complexity in resource-constrained designs.
What is the purpose of the SENSEA and SENSEB pins on the LTC2289IUP#PBF?
The SENSEA and SENSEB pins on the LTC2289IUP#PBF program the full-scale differential input range per channel: connecting to VCMA/VCMB selects ±0.5V, to VDD selects ±1V, or to an external reference (0.5V–1V) scales the range to ±VSENSE. This enables seamless adaptation to varying front-end gain without redesigning the analog signal chain.
LTC2289IUP#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 10
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 2
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.4V
- Voltage - Supply, Digital:
- 2.7V ~ 3.4V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-QFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2289IUP#PBF FAQ
1.How can I place an order for LTC2289IUP#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2289IUP#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2289IUP#PBF reliable?
The price and inventory of LTC2289IUP#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2289IUP#PBF is usually 5 days.
3.What payment methods are accepted for LTC2289IUP#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2289IUP#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2289IUP#PBF?
LTC2289IUP#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2289IUP#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2289IUP#PBF?
For technical support, including LTC2289IUP#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2289IUP#PBF requirements.
6.How does Aetrix verify that LTC2289IUP#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2289IUP#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2289IUP#PBF meets industry standards.
7.What is the process for return or replacement of LTC2289IUP#PBF?
All LTC2289IUP#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2289IUP#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2289IUP#PBF part is unused and in its original packaging.
Return procedure for LTC2289IUP#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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