My Inquiry
My Account
Analog Devices Inc. LTC2290IUP#TRPBF
- Part No.:
- LTC2290IUP#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LTC2290IUP#TRPBF.pdf
- Description:
- IC ADC 12BIT PIPELINED 64QFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,669
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2290IUP#TRPBF from Analog Devices (formerly Linear Technology) is a dual 12-bit, 10Msps low-power analog-to-digital converter operating from a single 3V supply (2.7V–3.4V), delivering 71.3dB SNR and 90dB SFDR at 5MHz input with 110dB channel isolation - designed for high-fidelity digitization in imaging and broadband communication front-ends.
For engineers reviewing the LTC2290IUP#TRPBF datasheet, LTC2290IUP#TRPBF pinout, LTC2290IUP#TRPBF application, or LTC2290IUP#TRPBF equivalent, key selection considerations include its dual-channel pipelined architecture, flexible ±0.5V/±1V differential input range, clock duty cycle stabilizer, multiplexed or separate 12-bit parallel output buses, and operation across –40°C to +85°C industrial temperature range.
Technical Context
The LTC2290IUP#TRPBF implements a six-stage CMOS pipelined ADC architecture per channel, with 5-cycle pipeline latency and integrated sample-and-hold featuring 575MHz full-power bandwidth. It supports independent or synchronized sampling via separate CLKA/CLKB inputs and includes on-chip 1.5V bandgap reference with programmable input range selection via SENSEA/SENSEB pins.
Its digital interface offers offset binary or 2's complement output format (selected by MODE pin), configurable output drivers (OVDD = 0.5V–3.6V), and dual shutdown modes (Nap: 15mW/channel; Shutdown: 2mW/channel). Crosstalk is specified at –110dB, and aperture jitter is 0.25LSBRMS with 0.2psRMS timing jitter.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in closed-loop control or spectral analysis. |
| Sample Rate | 10Msps maximum - enables real-time capture of baseband signals up to 5MHz Nyquist bandwidth in portable instrumentation. |
| SNR / SFDR | 71.3dB SNR and 90dB SFDR at 5MHz input - supports >11.5 effective number of bits (ENOB) for high-fidelity signal reconstruction. |
| Supply & Power | Single 3V analog supply (2.7V–3.4V); 120mW typical total power - reduces thermal load and simplifies power tree in space-constrained imaging modules. |
| Input Range | Differential ±0.5V or ±1V (pin-selectable via SENSEA/SENSEB) - allows optimization between dynamic range and noise floor for varying sensor outputs. |
| Channel Isolation | 110dB - prevents crosstalk-induced artifacts in dual-channel synchronous acquisition such as I/Q demodulation or stereo ultrasound beamforming. |
| Full-Power BW | 575MHz - preserves amplitude fidelity for wideband RF sampling applications without external anti-aliasing filter complexity. |
Pinout & Package
64-lead (9mm × 9mm) plastic QFN package with exposed pad (Pin 65 = GND), requiring soldering to PCB ground plane for thermal and electrical performance. Package thermal resistance θJA = 20°C/W; TJMAX = 125°C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AINA+, AINA– AINB+, AINB– |
Differential analog inputs (Ch A/B) | Accept ±0.5V or ±1V differential signals; require matched 100Ω source impedance for optimal SFDR and harmonic suppression. |
| CLKA, CLKB | Independent sampling clock inputs | Single-ended TTL/CMOS-compatible; enable asynchronous or synchronized dual-channel sampling with <50ns pulse width tolerance. |
| DA0–DA11, DB0–DB11 | 12-bit parallel digital outputs (Ch A/B) | Configurable as separate buses or multiplexed via MUX pin; support 0.5V–3.6V logic levels via OVDD supply. |
| SHDNA, SHDNB OEA, OEB |
Per-channel shutdown & output enable | Enable independent power gating: Nap mode (15mW/ch), Shutdown (2mW/ch), or full operation with tri-state control. |
| SENSEA, SENSEB VCMA, VCMB |
Reference programming & common-mode bias | Set input range (±0.5V/±1V) and provide 1.5V DC bias; VCMA/VCMB must be bypassed with ≥2.2µF ceramic capacitor to GND. |
| MODE, MUX | Output format & bus configuration control | MODE selects offset binary/2's complement and enables clock duty cycle stabilizer; MUX swaps DA/DB bus assignment for space-saving layout. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 12-bit pipelined ADC core | Enables simultaneous high-speed acquisition on two channels with 5-cycle deterministic latency - critical for time-aligned I/Q or stereo data capture. |
| Integrated clock duty cycle stabilizer | Allows high AC performance (71.3dB SNR) even with asymmetric clock waveforms (5%–95% duty cycle), eliminating need for external clock conditioning circuitry. |
| Programmable differential input range | ±0.5V or ±1V range selected per channel via SENSE pins - adapts to varying sensor output amplitudes without external gain stages. |
| 110dB channel-to-channel isolation | Minimizes inter-channel interference in multi-signal systems like phased-array ultrasound or dual-antenna receivers - verified at 5MHz input. |
| Flexible digital output interface | Separate or multiplexed 12-bit parallel buses with OVDD-adjustable voltage levels (0.5V–3.6V) - interfaces directly with FPGA I/O banks or microcontroller parallel ports. |
Applications
| Wireless Baseband Receiver | Medical Ultrasound Imaging |
|---|---|
|
Use Scenario: Digitizing I/Q downconverted RF signals in LTE/FDD-TDD infrastructure equipment with tight adjacent-channel rejection requirements. IC Role / Device Role / Timing Role: Dual-channel ADC capturing in-phase and quadrature components synchronously at 10Msps with <0.2psRMS jitter to preserve EVM and ACLR. Use Value: 90dB SFDR ensures spurious-free reception of weak signals adjacent to strong interferers; 110dB isolation prevents I/Q crosstalk-induced image distortion. |
Use Scenario: Beamformed echo signal acquisition in portable ultrasound scanners requiring compact, low-power, high-SNR digitization. IC Role / Device Role / Timing Role: Simultaneous sampling of multiple transducer channels with matched gain/offset and deterministic 5-cycle latency for real-time delay compensation. Use Value: ±0.3LSB INL and ±0.15LSB DNL ensure accurate tissue boundary detection; 120mW total power enables battery-operated handheld designs. |
| Spectral Analysis Instrumentation | Portable Test & Measurement Equipment |
|
Use Scenario: High-resolution frequency-domain analysis in handheld spectrum analyzers covering DC–5MHz with minimal harmonic distortion. IC Role / Device Role / Timing Role: Dual ADC performing real-time FFT on captured waveform segments, leveraging 71.3dB SNR and 575MHz input bandwidth for wide dynamic range. Use Value: 0.25LSBRMS transition noise and –110dB crosstalk preserve fine spectral features; internal reference eliminates external component count. |
Use Scenario: Multi-function data loggers acquiring sensor data (vibration, acoustic, thermal) with simultaneous dual-channel timestamped recording. IC Role / Device Role / Timing Role: Low-power dual ADC operating in Nap mode between triggers, waking on external event to capture synchronized analog snapshots. Use Value: 15mW Nap mode power extends battery life; flexible OVDD interface allows direct connection to 1.8V/3.3V logic without level shifters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel 12-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9233BCPZ-105 | 12-bit, 105Msps, single-channel only; requires external clock conditioner; higher power (340mW) | Targeted at high-speed single-stream applications (e.g., radar pulse capture), not dual-channel synchronous sampling | Select when >10Msps throughput is required and dual-channel correlation is unnecessary. |
| LTC2292IUP#TRPBF | Same pinout and feature set but 40Msps sample rate; higher power (220mW); identical –40°C to +85°C rating | Used where wider Nyquist bandwidth (up to 20MHz) is needed without changing PCB layout | Drop-in upgrade path if system design anticipates future bandwidth expansion beyond 5MHz. |
Compared with AD9233BCPZ-105 and LTC2292IUP#TRPBF, the LTC2290IUP#TRPBF uniquely balances dual-channel synchronization, ultra-low 120mW power, and industrial temperature operation - making it optimal for portable, battery-powered, and thermally constrained dual-signal acquisition systems.
Availability
LTC2290IUP#TRPBF is available at Aetrix Electronics and suitable for wireless infrastructure, medical imaging, portable instrumentation, and spectral analysis applications requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature grade performance.
Supply support for LTC2290IUP#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2290IUP#TRPBF belongs to ADI's high-speed precision ADC product line, engineered specifically for dual-channel, low-power, wide-dynamic-range digitization in space- and power-constrained embedded systems.
FAQ
What is the operating temperature range of the LTC2290IUP#TRPBF?
The LTC2290IUP#TRPBF is rated for industrial operation from –40°C to +85°C. This specification is guaranteed across all key AC and DC parameters including SNR, SFDR, INL, and DNL - enabling reliable deployment in outdoor base stations, portable medical devices, and factory-floor test equipment without derating.
Does the LTC2290IUP#TRPBF support single-ended analog inputs?
Yes, the LTC2290IUP#TRPBF supports single-ended inputs: drive AIN+ with the signal and tie AIN– to VCM (1.5V) or a quiet reference between 0.5V and 1.5V. However, harmonic distortion and INL degrade versus differential drive; SNR and DNL remain unaffected. For best performance, differential drive with matched ≤100Ω source impedance is recommended.
How does the clock duty cycle stabilizer in the LTC2290IUP#TRPBF improve system design?
The clock duty cycle stabilizer in the LTC2290IUP#TRPBF allows full 10Msps performance with input clock duty cycles from 5% to 95%, eliminating the need for external clock conditioners or precision clock generators. This reduces BOM cost and board area while maintaining 71.3dB SNR - especially valuable in systems using microcontroller-generated clocks or recovered data clocks.
Can the LTC2290IUP#TRPBF operate with different output voltage levels?
Yes, the LTC2290IUP#TRPBF supports configurable digital output voltage levels via the OVDD supply pin, which accepts 0.5V to 3.6V. This allows direct interfacing with 1.8V, 2.5V, or 3.3V logic families without level shifters - simplifying FPGA or microcontroller connectivity and reducing signal integrity risk in mixed-voltage systems.
What is the purpose of the SENSEA and SENSEB pins on the LTC2290IUP#TRPBF?
The SENSEA and SENSEB pins on the LTC2290IUP#TRPBF configure the differential input voltage range per channel: tying to VCMA/VCMB selects ±0.5V range; tying to VDD selects ±1V range; applying 0.5V–1V externally sets ±VSENSE. This enables precise matching to sensor output amplitude without external gain stages - preserving SNR and minimizing component count.
LTC2290IUP#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 10M
- Number of Inputs:
- 2
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.4V
- Voltage - Supply, Digital:
- 2.7V ~ 3.4V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-QFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2290IUP#TRPBF FAQ
1.How can I place an order for LTC2290IUP#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2290IUP#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2290IUP#TRPBF reliable?
The price and inventory of LTC2290IUP#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2290IUP#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2290IUP#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2290IUP#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2290IUP#TRPBF?
LTC2290IUP#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2290IUP#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2290IUP#TRPBF?
For technical support, including LTC2290IUP#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2290IUP#TRPBF requirements.
6.How does Aetrix verify that LTC2290IUP#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2290IUP#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2290IUP#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2290IUP#TRPBF?
All LTC2290IUP#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2290IUP#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2290IUP#TRPBF part is unused and in its original packaging.
Return procedure for LTC2290IUP#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2290IUP#TRPBF Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
