Analog Devices Inc. LTC2291IUP#PBF

Overview

LTC2291IUP#PBF from Analog Devices (formerly Linear Technology) is a dual 12-bit, 25Msps low-power analog-to-digital converter operating from a single 3V supply (2.7V–3.4V), delivering 71.4dB SNR and 90dB SFDR at 5MHz input with ±1V differential input range. It features integrated clock duty cycle stabilization, 110dB channel isolation at 100MHz, and flexible multiplexed or separate digital output buses for imaging and communications signal digitization.

For engineers reviewing the LTC2291IUP#PBF datasheet, LTC2291IUP#PBF pinout, LTC2291IUP#PBF application, or LTC2291IUP#PBF equivalent, key selection criteria include its 25Msps sample rate, dual-channel 12-bit resolution with no missing codes over temperature, 575MHz full-power bandwidth, and support for offset binary or 2's complement output formats via MODE pin configuration.

Technical Context

The LTC2291IUP#PBF implements a six-stage CMOS pipelined ADC architecture per channel, with pipeline latency of 5 cycles and aperture delay jitter of 0.2psRMS. It supports independent or synchronized sampling via separate CLKA/CLKB inputs and includes on-chip 1.5V common-mode bias (VCMA/VCMB) and programmable reference scaling via SENSEA/SENSEB pins.

Its digital interface uses two 12-bit parallel output buses (DA0–DA11 and DB0–DB11), each with dedicated overflow/underflow flags (OFA/OFB) and output enable/shutdown controls (OEA/OEB, SHDNA/SHDNB). The MODE pin selects both output format (offset binary or 2's complement) and clock duty cycle stabilizer activation.

Key Specifications

Pinout & Package

64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND), requiring soldering to PCB ground plane for thermal and electrical performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel ADC applications.

Compared with LTC2292IUP#PBF and AD9233BCPZ-25, the LTC2291IUP#PBF uniquely delivers dual-channel synchronization, ±1V programmable input range, and integrated clock duty cycle stabilization in a single 64-pin QFN-enabling compact, low-power, high-isolation signal acquisition without external support circuitry.

Availability

LTC2291IUP#PBF is available at Aetrix Electronics and suitable for wireless baseband receivers, portable ultrasound imaging systems, and spectral analyzer front-ends requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature grade (–40°C to +85°C).

Supply support for LTC2291IUP#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving precision instrumentation, communications, and industrial markets.

The LTC2291IUP#PBF belongs to ADI's high-speed dual ADC product line, engineered for demanding digitization tasks in portable test equipment, medical imaging, and broadband communications where channel matching, low power, and wide input bandwidth are critical.

FAQ

What is the operating temperature range for the LTC2291IUP#PBF?

The LTC2291IUP#PBF is specified for industrial temperature operation from –40°C to +85°C, as indicated by the "I" grade in the part number. This rating applies across all key AC and DC specifications including SNR, SFDR, INL, and DNL, ensuring reliable performance in harsh environments such as factory-floor instrumentation or outdoor communications equipment where the LTC2291IUP#PBF is deployed.

Does the LTC2291IUP#PBF support differential or single-ended analog inputs?

The LTC2291IUP#PBF is optimized for differential analog inputs (AINA+/AINA–, AINB+/AINB–) to achieve its rated 71.4dB SNR and 90dB SFDR. While single-ended drive is possible, it degrades harmonic distortion performance. The device includes dedicated REFH/REFL and SENSE pins to configure input ranges from ±0.5V to ±1V, and the LTC2291IUP#PBF datasheet specifies all AC performance metrics under differential drive conditions.

How does the MODE pin affect the LTC2291IUP#PBF's output behavior?

The MODE pin on the LTC2291IUP#PBF configures both output data format and clock duty cycle stabilizer (DCS) operation: grounding selects offset binary with DCS off; 1/3 VDD enables offset binary with DCS on; 2/3 VDD selects 2's complement with DCS on; and VDD chooses 2's complement with DCS off. This dual-function control allows the LTC2291IUP#PBF to adapt to host processor interface requirements while maintaining full performance with non-ideal clock sources.

Can the LTC2291IUP#PBF operate with separate clock inputs for each channel?

Yes, the LTC2291IUP#PBF supports fully independent sampling via CLKA and CLKB pins, enabling asynchronous acquisition of two signals. When synchronized operation is needed, tying CLKA and CLKB together with MUX = high routes Channel A to DA0–DA11 and Channel B to DB0–DB11. This flexibility makes the LTC2291IUP#PBF suitable for time-interleaved or correlated dual-channel applications without external clock distribution circuitry.

What power supply configurations does the LTC2291IUP#PBF require?

The LTC2291IUP#PBF requires two supplies: VDD (2.7V–3.4V) for analog circuitry and OVDD (0.5V–3.6V) for digital output drivers. VDD powers the ADC cores, references, and S/H circuits, while OVDD sets logic levels for DA0–DA11 and DB0–DB11 outputs-allowing direct interfacing to 1.8V, 2.5V, or 3.3V FPGAs or processors. The LTC2291IUP#PBF draws 50mA from VDD and scalable current from OVDD depending on load and voltage.