Analog Devices Inc. LTC2292IUP#PBF
- Part No.:
- LTC2292IUP#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LTC2292IUP#PBF.pdf
- Description:
- IC ADC 12BIT PIPELINED 64QFN
- Quantity:
- Payment:

- Shipping:

Inventory:458
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Product details
Overview
LTC2292IUP#PBF from Analog Devices (formerly Linear Technology) is a dual 12-bit, 40Msps low-power analog-to-digital converter operating from a single 3V supply. It delivers 71.4dB SNR and 90dB SFDR at 5MHz input, supports ±0.5V to ±1V differential input range, and features 110dB channel isolation at 100MHz - ideal for high-fidelity spectral analysis and portable instrumentation signal chains.
For engineers reviewing the LTC2292IUP#PBF datasheet, LTC2292IUP#PBF pinout, LTC2292IUP#PBF application, or LTC2292IUP#PBF equivalent, key selection criteria include its 40Msps sample rate, dual-channel 12-bit resolution with <0.25LSBRMS transition noise, flexible output bus multiplexing, and integrated clock duty cycle stabilizer enabling robust timing across wide-duty-cycle clocks.
Technical Context
The LTC2292IUP#PBF implements a six-stage CMOS pipelined ADC architecture per channel, delivering 5-cycle pipeline latency and supporting independent or synchronized sampling via separate CLKA/CLKB inputs. Its internal 1.5V reference buffer (VCMA/VCMB), programmable SENSEA/SENSEB pins, and MODE-selectable offset binary/two's complement output format enable precise input range and data format control.
It integrates a clock duty cycle stabilizer (DCS) that maintains high AC performance across 35%–65% input clock duty cycles, and supports three power states: active (235mW), nap mode (15mW per channel), and shutdown (2mW per channel), all managed via SHDNA/SHDNB and OEA/OEB pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in closed-loop control or imaging systems. |
| Sample Rate | 40Msps - enables Nyquist-limited bandwidth up to 20MHz, suitable for IF sampling in broadband receivers. |
| SNR @ 5MHz | 71.4dBFS - provides >70dB effective number of bits (ENOB ≈ 11.6) for high-fidelity digitization of baseband or intermediate-frequency signals. |
| SFDR @ 5MHz | 90dBc - suppresses spurious harmonics sufficiently for demanding communications applications like LTE/WiMAX channel analysis. |
| Channel Isolation | 110dB at 100MHz - minimizes crosstalk between simultaneous A/B channel acquisitions in dual-sensor or I/Q demodulation systems. |
| Power Dissipation | 235mW at 40Msps (both channels active) - enables thermally constrained portable designs without forced cooling. |
| Input Bandwidth | 575MHz full-power - supports direct RF sampling of VHF/UHF bands when paired with appropriate front-end filtering and drive capability. |
Pinout & Package
64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AINA+, AINA– AINB+, AINB– | Differential analog inputs (Ch A & Ch B) | Accept ±0.5V to ±1V differential swing; require matched layout and termination for optimal CMRR and harmonic distortion. |
| CLKA, CLKB | Independent sampling clock inputs | Single-ended TTL/CMOS-compatible; rising-edge triggered; support asynchronous or synchronous dual-channel capture. |
| DA0–DA11, DB0–DB11 | 12-bit parallel digital outputs (Ch A & Ch B) | Configurable as separate buses or multiplexed via MUX pin; output voltage swing referenced to OVDD (0.5V–3.6V). |
| SENSEA, SENSEB | Analog input range programming pins | Set full-scale range: tied to VCMA/VCMB → ±0.5V; to VDD → ±1V; external voltage → ±VSENSE. |
| MODE | Output format & DCS control | GND = offset binary + DCS off; 1/3 VDD = offset binary + DCS on; 2/3 VDD = two's complement + DCS on. |
| SHDNA, SHDNB OEA, OEB | Per-channel shutdown & output enable | Four combinations define active, high-Z, nap (reduced power), and sleep (minimal power) modes per channel. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 12-bit ADC cores | Enables simultaneous sampling of I/Q signals or dual sensor inputs without interleaving artifacts or timing skew. |
| Flexible 0.5V–3.6V OVDD output supply | Allows direct interface to 1.8V, 2.5V, or 3.3V logic families without level shifters - reduces BOM count and board area. |
| Integrated clock duty cycle stabilizer | Eliminates need for external clock conditioning circuitry; maintains >70dB SNR even with 40%–60% duty cycle clocks from PLLs or crystal oscillators. |
| 110dB channel-to-channel isolation | Ensures accurate dual-channel measurements in spectral analyzers or phased-array receivers where leakage would corrupt dynamic range. |
| Programmable input common-mode range | Supports both transformer-coupled (±0.5V) and op-amp-driven (±1V) front ends - simplifies analog signal chain design across multiple platforms. |
Applications
| Wireless Communication Receiver | Portable Spectrum Analyzer |
|---|---|
Use Scenario: Digitizing 0–20MHz IF signals from quadrature downconverters in LTE femtocell base stations. IC Role / Device Role / Timing Role: Dual-channel ADC captures I and Q paths simultaneously with matched gain/phase and sub-1ps inter-channel jitter. Use Value: 90dB SFDR prevents adjacent-channel interference masking weak signals; 40Msps sample rate satisfies 3GPP bandwidth requirements. | Use Scenario: Real-time frequency-domain analysis in handheld test equipment with battery-powered operation. IC Role / Device Role / Timing Role: High-SNR digitizer feeding FFT engine; low 235mW power enables >4-hour runtime on Li-ion pack. Use Value: 71.4dB SNR ensures accurate amplitude measurement of low-level harmonics; 575MHz input BW supports preselector-less 100MHz span. |
| Medical Ultrasound Beamformer | Industrial Imaging System |
Use Scenario: Sampling echo return signals from multi-element transducer arrays in portable ultrasound devices. IC Role / Device Role / Timing Role: Dual ADC per receive channel pair; synchronized CLKA/CLKB enables coherent beamforming across 128+ channels. Use Value: 110dB channel isolation prevents cross-talk between adjacent beam paths; <0.25LSBRMS noise preserves contrast resolution in B-mode images. | Use Scenario: Capturing high-fidelity line-scan camera output in automated optical inspection (AOI) systems. IC Role / Device Role / Timing Role: Digitizing analog video output from CCD/CMOS sensors at pixel rates up to 40Mpix/s. Use Value: Offset binary output format simplifies FPGA-based pixel alignment logic; OVDD flexibility allows direct connection to image processor I/O banks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9233BCPZ-40 | 12-bit, 40Msps, single-channel only; requires two units for dual-channel use; higher 320mW power; no integrated DCS. | Lacks native dual-channel synchronization and channel isolation spec; needs external clock cleanup for same SNR stability. | Select when board space permits discrete channel replication and system-level clock conditioning is already available. |
| LTC2297IUP#PBF | 14-bit, 40Msps dual ADC; 2-bit higher resolution; 315mW power; identical pinout and feature set except resolution and SNR (74.5dB). | Provides 3dB higher dynamic range for applications requiring finer amplitude discrimination (e.g., high-end radar). | Select when ENOB > 12 is mandatory and 75mW extra power budget is acceptable. |
Compared with AD9233BCPZ-40, LTC2292IUP#PBF saves PCB area and eliminates inter-channel skew risk via monolithic dual-core integration; compared with LTC2297IUP#PBF, it trades 2-bit resolution for 33% lower power and cost - ideal for portable or cost-sensitive 12-bit systems.
Availability
LTC2292IUP#PBF is available at Aetrix Electronics and suitable for wireless infrastructure, portable instrumentation, and industrial imaging systems requiring stable component supply, extended temperature operation (–40°C to +85°C), and long-term production continuity.
Supply support for LTC2292IUP#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets.
The LTC2292 belongs to ADI's high-speed precision ADC product line, engineered for applications demanding wide bandwidth, low noise, and dual-channel coherence - especially in portable, battery-constrained, and spectrally demanding systems.
FAQ
What is the guaranteed operating temperature range for the LTC2292IUP#PBF?
The LTC2292IUP#PBF is specified for industrial temperature operation from –40°C to +85°C. This is confirmed by the "I" grade suffix in the part number and validated across all AC/DC specifications in the datasheet, including SNR, SFDR, INL, and power consumption.
Does the LTC2292IUP#PBF support single-ended analog inputs?
Yes, the LTC2292IUP#PBF supports single-ended analog inputs, though differential drive is recommended for optimal harmonic distortion and CMRR. The datasheet specifies single-ended input common-mode range as 0.5V to 2.0V and confirms functionality with reduced SFDR performance versus differential mode.
How does the MODE pin affect the LTC2292IUP#PBF's output data format and clock handling?
The MODE pin configures both output format and clock duty cycle stabilizer (DCS) state. Ground selects offset binary + DCS off; 1/3 VDD selects offset binary + DCS on; 2/3 VDD selects two's complement + DCS on; VDD selects two's complement + DCS off. This dual function is explicitly defined in the Pin Functions section of the LTC2292IUP#PBF datasheet.
Can the LTC2292IUP#PBF's digital output bus be shared between both channels?
Yes, the LTC2292IUP#PBF supports multiplexed output via the MUX pin. When MUX = Low, Channel A data appears on DB0–DB11/OFB and Channel B on DA0–DA11/OFA; when MUX = High, the mapping swaps. This allows both channels to share one 12-bit data bus and one overflow flag line, reducing FPGA I/O count.
What is the absolute maximum rating for the analog supply voltage (VDD) of the LTC2292IUP#PBF?
The absolute maximum rating for VDD on the LTC2292IUP#PBF is 4V, as stated in the Absolute Maximum Ratings table. Operation above 3.4V (maximum recommended) risks parametric degradation, while exceeding 4V may cause permanent damage. All DC specs are guaranteed within 2.7V to 3.4V.
LTC2292IUP#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 40M
- Number of Inputs:
- 2
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.4V
- Voltage - Supply, Digital:
- 2.7V ~ 3.4V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-QFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2292IUP#PBF FAQ
1.How can I place an order for LTC2292IUP#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2292IUP#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2292IUP#PBF reliable?
The price and inventory of LTC2292IUP#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2292IUP#PBF is usually 5 days.
3.What payment methods are accepted for LTC2292IUP#PBF?
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4.How is shipping managed for LTC2292IUP#PBF?
LTC2292IUP#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2292IUP#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2292IUP#PBF?
For technical support, including LTC2292IUP#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2292IUP#PBF requirements.
6.How does Aetrix verify that LTC2292IUP#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2292IUP#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2292IUP#PBF meets industry standards.
7.What is the process for return or replacement of LTC2292IUP#PBF?
All LTC2292IUP#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2292IUP#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2292IUP#PBF part is unused and in its original packaging.
Return procedure for LTC2292IUP#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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