Analog Devices Inc. LTC2299IUP#PBF

Overview

LTC2299IUP#PBF from Analog Devices (formerly Linear Technology) is a dual 14-bit, 80Msps pipelined analog-to-digital converter operating from a single 3V supply (2.7V–3.4V), delivering 73dB SNR and 90dB SFDR at 70MHz input frequency, with 110dB channel isolation at 100MHz - deployed in high-performance communications receivers and medical ultrasound imaging front ends.

For engineers reviewing the LTC2299IUP#PBF datasheet, LTC2299IUP#PBF pinout, LTC2299IUP#PBF application, or LTC2299IUP#PBF equivalent, key selection considerations include dual-channel AC performance at Nyquist-plus frequencies, flexible 1VP-P to 2VP-P differential input range, clock duty cycle stabilization, multiplexed or independent digital output bus configuration, and −40°C to +85°C industrial temperature grade.

Technical Context

The LTC2299IUP#PBF implements a six-stage CMOS pipelined ADC architecture with integrated sample-and-hold, internal 1.5V reference, and programmable input common-mode bias (VCMA/VCMB). Each channel features independent shutdown (SHDNA/SHDNB) and output enable (OEA/OEB) controls, plus shared MODE pin for output format (offset binary/2's complement) and clock duty cycle stabilizer activation.

It supports differential analog inputs (AINA±, AINB±) with ±0.5V to ±1V full-scale range, 575MHz full-power bandwidth, and aperture jitter of 0.2psRMS. Digital outputs are LVCMOS-compatible with OVDD programmable from 0.5V to 3.6V, enabling direct interface to FPGAs or ASICs across multiple logic families.

Key Specifications

Pinout & Package

64-lead (9mm × 9mm) plastic QFN package with exposed thermal pad (Pin 65 = GND); RoHS-compliant, lead-free finish (#PBF).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, high-speed ADC applications.

Compared with AD9233BCPZ-80 and LTC2284IUP#PBF, the LTC2299IUP#PBF uniquely balances 14-bit resolution, dual-channel integration, 73dB SNR at 70MHz, and 444mW power in an industrial-grade QFN - making it optimal for space-constrained, thermally sensitive, and high-isolation dual-sampling applications.

Availability

LTC2299IUP#PBF is available at Aetrix Electronics and suitable for wireless infrastructure, medical imaging, and portable test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LTC2299IUP#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.

The LTC2299IUP#PBF belongs to ADI's high-speed precision ADC product line, engineered specifically for demanding wideband digitization in communications infrastructure and medical diagnostics where dual-channel coherence, low jitter, and thermal stability are critical.

FAQ

What is the operating temperature range for the LTC2299IUP#PBF?

The LTC2299IUP#PBF is specified for industrial operation from −40°C to +85°C (I-grade), validated across all AC and DC parameters per the datasheet. This range supports deployment in base station outdoor units, ultrasound carts, and field-test instruments without derating. The LTC2299IUP#PBF uses the same silicon die as the C-grade (0°C to 70°C) and UP-package construction, with extended characterization confirming performance stability over the full I-grade span.

Does the LTC2299IUP#PBF support single-ended analog inputs?

Yes, the LTC2299IUP#PBF supports single-ended inputs: drive AIN+ with the signal and tie AIN− to 1.5V (VCMA or VCMB). However, harmonic distortion and INL degrade versus differential drive; SNR and DNL remain unaffected. The LTC2299IUP#PBF datasheet Figure 4 shows a recommended op-amp-based single-ended-to-differential circuit, and Figure 5 illustrates direct single-ended connection with appropriate impedance matching.

How does the clock duty cycle stabilizer function in the LTC2299IUP#PBF?

The LTC2299IUP#PBF clock duty cycle stabilizer (enabled via MODE pin at 1/3 VDD or 2/3 VDD) corrects asymmetric input clocks internally, maintaining 73dB SNR and 90dB SFDR across 30%–70% duty cycles. It eliminates external duty cycle correction ICs or delay-locked loops, reducing BOM count and board area. Performance data in Figure 2299 G13 confirms stable SNR/SFDR with DCS enabled versus >3dB degradation when disabled at extreme duty cycles.

Can both channels of the LTC2299IUP#PBF share the same digital output bus?

Yes, the LTC2299IUP#PBF supports multiplexed output via the MUX pin: when MUX = LOW, Channel A outputs appear on DB0–DB13/OFB and Channel B on DA0–DA13/OFA; when MUX = HIGH, the mapping reverses. This allows both channels to time-share a single 14-bit data bus, halving FPGA I/O usage. Timing diagrams in Figures 2299 TD02 and the "Multiplexed Digital Output Bus Timing" section confirm deterministic 1-cycle alternation without bus contention.

What is the purpose of the SENSEA and SENSEB pins on the LTC2299IUP#PBF?

The SENSEA and SENSEB pins on the LTC2299IUP#PBF program the full-scale input range per channel: tying to VCMA/VCMB selects ±0.5V (1VP-P), to VDD selects ±1V (2VP-P), or to an external 0.5V–1V reference selects ±V_SENSE. This configures the internal gain stage and determines LSB size (0.122mV/LSB for 2VP-P range). The LTC2299IUP#PBF datasheet Table "Analog Input Range" and Pin Functions section (page 8) specify these relationships and bypassing requirements.