Analog Devices Inc. LTC2310CMSE-16#PBF

Overview

LTC2310CMSE-16#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, 2 Msps successive approximation register (SAR) analog-to-digital converter with differential inputs, ±3 LSB typical INL, 82 dB SNR at 500 kHz, and integrated 4.096 V temperature-compensated reference. It operates from a single 3.3 V or 5 V supply and delivers no missing codes across its full 16-bit resolution-ideal for high-speed data acquisition in optical networking and motor control systems.

For engineers reviewing the LTC2310CMSE-16#PBF datasheet, LTC2310CMSE-16#PBF pinout, LTC2310CMSE-16#PBF application, or LTC2310CMSE-16#PBF equivalent, key selection criteria include guaranteed operation from 0°C to 70°C, CMOS/LVDS serial interface configurability, differential input common mode range of 0 V to VDD, and low 35 mW power dissipation at 5 V.

Technical Context

The LTC2310CMSE-16#PBF implements a SAR architecture with no cycle latency, enabling deterministic timing for real-time control loops. Its internal 4.096 V reference exhibits ≤20 ppm/°C drift and supports external 1.25 V reference injection via REFIN, while the analog front-end accepts differential inputs up to 8 V_P-P with 85 dB CMRR at 500 kHz.

Digital interface flexibility is provided through a single CMOS/LVDS select pin (Pin 10), allowing configuration for either CMOS-level I/O (1.8 V–2.5 V OVDD) or LVDS differential signaling (100 Ω termination). Conversion is initiated by a TTL-compatible CNV pulse, and output data is clocked MSB-first on SCK falling edges with t_CONV = 220 ns and t_READOUT = 250 ns.

Key Specifications

Pinout & Package

Package: 16-lead plastic MSOP (4 mm × 5 mm), exposed pad (Pin 17) soldered to ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed SAR ADC applications.

Compared with ADS8860IDRCT and AD7960BCPZ-RL7, the LTC2310CMSE-16#PBF uniquely balances 2 Msps throughput, integrated 4.096 V reference, differential input flexibility, and LVDS/CMOS configurability in a compact MSOP-making it optimal for space- and power-sensitive industrial data loggers.

Availability

LTC2310CMSE-16#PBF is available at Aetrix Electronics and suitable for high-speed data acquisition systems, optical networking modules, and multiphase motor control applications requiring stable component supply and commercial-temperature-grade reliability.

Supply support for LTC2310CMSE-16#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies.

The LTC2310-16 product line was designed for high-speed, high-accuracy data acquisition in space-constrained industrial, communications, and test equipment-emphasizing low power, integrated references, and flexible digital interfaces.

FAQ

What is the maximum sampling rate supported by the LTC2310CMSE-16#PBF?

The LTC2310CMSE-16#PBF supports a maximum sampling rate of 2 Msps with no cycle latency. This is achieved using a successive approximation register architecture that completes conversion and readout within 470 ns (t_CONV + t_READOUT). The specification is guaranteed over the full 0°C to 70°C operating temperature range and applies to both CMOS and LVDS interface modes. At this rate, the LTC2310CMSE-16#PBF maintains 82 dB SNR and ±3 LSB INL typical performance.

Does the LTC2310CMSE-16#PBF require an external reference voltage?

No, the LTC2310CMSE-16#PBF does not require an external reference voltage-it integrates a precision 4.096 V temperature-compensated reference with ≤20 ppm/°C drift. However, it provides a 1.25 V buffered REFIN pin that can accept an external reference or disable the internal REFOUT buffer. When REFIN is grounded, the internal reference buffer is disabled and REFOUT becomes an input capable of accepting 1.25 V to VDD, giving designers flexibility for system-level reference sharing.

How is the digital interface mode selected on the LTC2310CMSE-16#PBF?

The digital interface mode on the LTC2310CMSE-16#PBF is selected via the CMOS/LVDS pin (Pin 10): grounding it configures CMOS I/O (1.8 V–2.5 V OVDD); connecting it to OVDD selects LVDS mode; leaving it floating enables low-power LVDS. This single-pin configuration eliminates external mode-selection logic. In CMOS mode, only SDO+ and SCK+ are used; in LVDS mode, differential pairs SDO+/SDO– and SCK+/SCK– must be terminated with 100 Ω resistors at the receiver.

What are the power consumption characteristics of the LTC2310CMSE-16#PBF in different operating modes?

The LTC2310CMSE-16#PBF consumes 35 mW at 5 V and 2 Msps (active mode), 14 mW in nap mode after conversion completion, and just 0.5 µW in sleep mode. Power scales with sample rate and supply voltage-e.g., at 3.3 V and 2 Msps, active power drops to 25 mW. These low quiescent currents are enabled by dedicated nap and sleep control states, making the LTC2310CMSE-16#PBF suitable for battery-powered instrumentation where duty-cycled acquisition is employed.

Can the LTC2310CMSE-16#PBF interface directly with a 1.8 V FPGA I/O bank?

Yes, the LTC2310CMSE-16#PBF can interface directly with a 1.8 V FPGA I/O bank by setting OVDD = 1.8 V and configuring the CMOS/LVDS pin for CMOS mode. The digital I/O specifications guarantee VIH ≥ 0.8 × OVDD (≥1.44 V) and VOL ≤ 0.2 × OVDD (≤0.36 V), ensuring robust logic-level compatibility. SDO output drive strength meets FPGA input requirements, and the 5 pF digital input capacitance minimizes loading-no level translators or series resistors are needed for reliable 64 MHz SCK operation.