Analog Devices Inc. LTC2321CUFD-12#TRPBF
- Part No.:
- LTC2321CUFD-12#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC2321CUFD-12#TRPBF.pdf
- Description:
- IC ADC 12BIT SAR 28QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2321CUFD-12#TRPBF from Analog Devices is a dual, 12-bit + sign successive approximation register (SAR) analog-to-digital converter with differential inputs, 2 Msps per channel throughput, ±0.5 LSB typical INL, 73 dB SNR at 500 kHz, and integrated 4.096 V temperature-compensated reference. It operates from single 3.3 V or 5 V supply and supports CMOS or LVDS serial interface - ideal for high-speed data acquisition in motor control and optical networking systems.
For engineers reviewing the LTC2321CUFD-12#TRPBF datasheet, LTC2321CUFD-12#TRPBF pinout, LTC2321CUFD-12#TRPBF application, or LTC2321CUFD-12#TRPBF equivalent, key selection criteria include guaranteed 12-bit no-missing-codes performance, wide input common mode range (0 V to VDD), low-power nap/sleep modes (5 µW), and dual-channel zero-cycle-latency conversion timing.
Technical Context
The LTC2321CUFD-12#TRPBF implements two independent SAR ADC cores, each with dedicated sample-and-hold, 13-bit CDAC, and differential comparator. Its transfer function delivers 13-bit resolution across ±REFOUT (2 × 4.096 V full-scale) in fully differential mode, or 12-bit resolution over reduced spans in pseudo-differential configurations - all without hardware reconfiguration.
It features dual independent reference buffers (REFOUT1/REFOUT2), configurable I/O interface (CMOS/LVDS via Pin 25), skew-matched CLKOUT for deterministic SDO timing, and internal LDOs supplying VBYP1/VBYP2 (1.6 V). Absolute maximum ratings include 125°C junction temperature and 6 V VDD, supporting industrial and automotive environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit + sign (13-bit effective in fully differential mode), enabling precise bipolar signal digitization with inherent sign bit. |
| Sampling Rate | 2 Msps per channel, supporting real-time capture of signals up to 10 MHz linear bandwidth. |
| INL | ±0.5 LSB typical, ensuring accurate end-point linearity critical for closed-loop control feedback. |
| SNR | 73 dB typical at fIN = 500 kHz, delivering >12 ENOB for high-fidelity signal reconstruction. |
| Reference | Internal 4.096 V ±0.2% (20 ppm/°C max), eliminating external reference component count and layout complexity. |
| Power Dissipation | 30 mW per channel at 2 Msps (5 V), scalable down to 5 µW in sleep mode for power-constrained systems. |
| Supply Range | VDD: 4.75–5.25 V or 3.13–3.47 V; OVDD: 1.71–2.63 V, enabling interoperability with 1.8 V/2.5 V FPGA/CPLD I/O domains. |
Pinout & Package
Package: 28-lead (4 mm × 5 mm) plastic QFN (UFD) with exposed pad (Pin 29) soldered to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Pins 1, 8) | Analog power supply | Single 3.3 V or 5 V rail powering ADC core and reference buffers; requires local 10 µF + 0.1 µF bypassing. |
| AIN1+, AIN1– (Pins 7, 6); AIN2+, AIN2– (Pins 2, 3) | Differential analog inputs (Channel 1 & 2) | Support fully differential, pseudo-differential unipolar/bipolar inputs with 0 V to VDD common mode range - no configuration required. |
| CNV (Pin 9) | Conversion start trigger | Falling-edge initiated; zero-cycle latency enables deterministic timing for synchronized multi-channel sampling. |
| REFOUT1/REFOUT2 (Pins 12, 26) | Reference buffer outputs | Nominally 4.096 V; decoupled with 10 µF + 0.1 µF capacitors; disable via REFINT (Pin 28) for external reference use. |
| SCK+, SCK– (Pins 21, 22) | Serial clock input | Differential LVDS or single-ended CMOS clock (up to 64 MHz); determines conversion result readout timing. |
| SDO1+/SDO1–, SDO2+/SDO2– (Pins 15/16, 19/20) | Serial data outputs (Ch1 & Ch2) | MSB-first, SPI-compatible output; LVDS mode requires 100 Ω differential termination at receiver (e.g., FPGA). |
| CLKOUT+, CLKOUT– (Pins 17, 18) | Skew-matched output clock | Provides phase-aligned clock to latch SDO data at receiver - eliminates setup/hold uncertainty in high-speed interfaces. |
| CMOS/LVDS (Pin 25) | I/O interface mode select | GND = CMOS; OVDD = LVDS; floating = low-power LVDS - configures driver strength and termination behavior. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent SAR ADCs | Enables simultaneous sampling of two channels with matched aperture delay (≤500 ps), critical for phase-sensitive applications like motor current sensing. |
| Wide input common mode range (0 V to VDD) | Eliminates need for level-shifting circuitry when interfacing with op-amp drivers operating rail-to-rail or beyond. |
| Onboard 4.096 V reference (20 ppm/°C max) | Reduces BOM count and improves system-level accuracy stability without external trimming or calibration. |
| Zero-cycle latency conversion | Allows immediate readout after CNV edge - essential for real-time control loops requiring minimal processing delay. |
| Configurable CMOS/LVDS I/O | Supports direct connection to 1.8 V/2.5 V FPGAs or high-noise-immunity LVDS receivers without level translators. |
| Nap/sleep power modes (5 µW) | Extends battery life in portable instrumentation and enables rapid wake-up (<10 ms REFOUT stabilization) for burst-mode acquisition. |
Applications
| High-Speed Motor Control | Optical Network Monitoring |
|---|---|
|
Use Scenario: Real-time sampling of dual-phase motor currents and back-EMF in servo drives operating at >20 kHz PWM frequencies. IC Role / Device Role / Timing Role: Dual-channel simultaneous sampling ADC providing synchronized current/voltage feedback with ≤500 ps inter-channel matching. Use Value: Enables precise field-oriented control (FOC) with <12-bit linearity and 2 Msps throughput - reducing torque ripple and improving efficiency. |
Use Scenario: Digitizing photodiode output signals from DWDM channel monitors in 100G+ coherent transceivers. IC Role / Device Role / Timing Role: High-SNR ADC capturing low-amplitude optical power variations while rejecting common-mode noise from laser bias supplies. Use Value: 73 dB SNR and 85 dB CMRR ensure accurate optical power measurement across temperature, supporting dynamic gain control algorithms. |
| Industrial Data Acquisition | Automotive Battery Management |
|
Use Scenario: Multi-sensor monitoring (vibration, temperature, strain) in predictive maintenance gateways with isolated front-end amplifiers. IC Role / Device Role / Timing Role: Dual ADC accepting pseudo-differential unipolar/bipolar inputs directly from instrumentation amps - no external configuration needed. Use Value: Wide 0 V to VDD common mode range relaxes op-amp supply requirements, simplifying isolated analog front-end design. |
Use Scenario: Cell voltage and temperature sampling in high-voltage EV battery packs under harsh EMI conditions. IC Role / Device Role / Timing Role: Robust ADC with LVDS interface and 125°C operation, immune to ground bounce and switching noise in high-power inverters. Use Value: Guaranteed operation to 125°C and 100 Ω LVDS termination provide reliable cell monitoring in under-hood environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7903BRUZ | 16-bit, 1 Msps, no internal reference, SPI-only (no LVDS), 24-lead TSSOP | Higher resolution but lower speed; requires external reference and level-shifting for 1.8 V logic | Choose AD7903BRUZ when 16-bit precision outweighs speed and interface flexibility needs. |
| ADS8860IRGET | 16-bit, 1 Msps, single-channel, internal reference, SPI, 20-lead VQFN | Single-channel only; lacks dual simultaneous sampling and LVDS support | Use ADS8860IRGET for cost-sensitive, lower-throughput applications where channel count is not critical. |
Compared with AD7903BRUZ and ADS8860IRGET, the LTC2321CUFD-12#TRPBF uniquely combines dual-channel 2 Msps throughput, integrated LVDS interface, on-chip 4.096 V reference, and zero-cycle latency - making it optimal for time-critical, noise-sensitive, multi-channel acquisition systems.
Availability
LTC2321CUFD-12#TRPBF is available at Aetrix Electronics and suitable for high-speed motor control, optical network monitoring, and industrial data acquisition requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC2321CUFD-12#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC2321CUFD-12#TRPBF belongs to the Linear Technology high-speed precision ADC product line, designed specifically for demanding data acquisition systems requiring low noise, high throughput, and robust interface flexibility in harsh environments.
FAQ
What is the operating temperature range for the LTC2321CUFD-12#TRPBF?
The LTC2321CUFD-12#TRPBF is rated for 0°C to 70°C ambient operation (C-grade). This is confirmed by the "CUFD" suffix in the part number and the order information table listing "0°C to 70°C" for LTC2321CUFD-12#TRPBF. It meets specifications across this full range, including ±0.5 LSB INL and 73 dB SNR.
Does the LTC2321CUFD-12#TRPBF require external reference components?
No - the LTC2321CUFD-12#TRPBF integrates two temperature-compensated 4.096 V reference buffers (REFOUT1/REFOUT2) with 20 ppm/°C max drift. External decoupling (10 µF + 0.1 µF) is required, but no external reference IC or resistor network is needed unless using an external reference via REFINT pin grounding.
How does the LTC2321CUFD-12#TRPBF support both CMOS and LVDS interfaces?
The LTC2321CUFD-12#TRPBF uses Pin 25 (CMOS/LVDS) to configure interface mode: grounded for CMOS (single-ended SDO/CLKOUT), tied to OVDD for standard LVDS, or left floating for low-power LVDS. SCK/SDO/CLKOUT pins are internally configured for the selected mode - no external resistors needed for CMOS, 100 Ω differential termination required for LVDS.
What is the significance of "12-bit + sign" resolution in the LTC2321CUFD-12#TRPBF?
"12-bit + sign" means the LTC2321CUFD-12#TRPBF outputs a 13-bit two's complement code where the MSB is the sign bit. In fully differential mode, it resolves ±REFOUT into 8192 codes (13-bit effective), enabling true bipolar measurement from –4.096 V to +4.096 V with inherent sign indication and no offset calibration.
Can the LTC2321CUFD-12#TRPBF operate from a 3.3 V supply?
Yes - the LTC2321CUFD-12#TRPBF supports VDD = 3.13 V to 3.47 V (3.3 V nominal) and OVDD = 1.71 V to 2.63 V (1.8 V or 2.5 V compatible). Power dissipation drops to 37–58 mW per channel at 2 Msps in CMOS mode, and sleep current remains 5 µW, making it suitable for low-voltage embedded systems.
LTC2321CUFD-12#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 2M
- Number of Inputs:
- 2
- Input Type:
- Differential, Pseudo-Differential
- Data Interface:
- LVDS - Serial, Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 3.13V ~ 3.47V, 5V
- Voltage - Supply, Digital:
- 3.13V ~ 3.47V, 5V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 28-QFN (4x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2321CUFD-12#TRPBF FAQ
1.How can I place an order for LTC2321CUFD-12#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2321CUFD-12#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2321CUFD-12#TRPBF reliable?
The price and inventory of LTC2321CUFD-12#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2321CUFD-12#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2321CUFD-12#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2321CUFD-12#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2321CUFD-12#TRPBF?
LTC2321CUFD-12#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2321CUFD-12#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2321CUFD-12#TRPBF?
For technical support, including LTC2321CUFD-12#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2321CUFD-12#TRPBF requirements.
6.How does Aetrix verify that LTC2321CUFD-12#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2321CUFD-12#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2321CUFD-12#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2321CUFD-12#TRPBF?
All LTC2321CUFD-12#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2321CUFD-12#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2321CUFD-12#TRPBF part is unused and in its original packaging.
Return procedure for LTC2321CUFD-12#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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