Analog Devices Inc. LTC2321CUFD-14#PBF
- Part No.:
- LTC2321CUFD-14#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC2321CUFD-14#PBF.pdf
- Description:
- IC ADC 14BIT SAR 28QFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,891
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2321CUFD-14#PBF from Analog Devices is a dual-channel, 14-bit + sign successive approximation register (SAR) analog-to-digital converter with differential inputs, 2 Msps per channel throughput, ±1 LSB typical INL, 80 dB SNR at 500 kHz, and integrated 2.048 V / 4.096 V temperature-compensated reference. It operates from a single 3.3 V or 5 V supply and supports CMOS or LVDS serial interface for high-speed data acquisition in motor control and optical networking systems.
For engineers reviewing the LTC2321CUFD-14#PBF datasheet, LTC2321CUFD-14#PBF pinout, LTC2321CUFD-14#PBF application, or LTC2321CUFD-14#PBF equivalent, key selection criteria include guaranteed no-missing-codes performance at 14 bits, wide input common mode range (0 V to VDD), low-power nap/sleep modes (5 µW), and dual-channel simultaneous sampling with no-cycle latency.
Technical Context
The LTC2321CUFD-14#PBF implements two independent SAR ADC cores sharing a common reference architecture and digital interface. Each channel features a fully differential sample-and-hold with 10 pF input capacitance and 15 Ω switch on-resistance, enabling direct connection to precision signal sources without external buffering.
Its timing architecture uses a falling-edge–triggered CNV input to initiate conversion with 220 ns typical conversion time and skew-matched CLKOUT output for deterministic data capture. The internal reference buffers (REFOUT1/REFOUT2) deliver 4.096 V ±0.2% with ≤20 ppm/°C drift and support external reference override via REFINT pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit + sign (15-bit two's complement output); enables digitization of ±REFOUT full-scale differential input with overrange capability. |
| Sampling Rate | 2 Msps per channel; supports real-time acquisition of signals up to 10 MHz –3dB bandwidth with <3 ns transient response. |
| INL | ±1 LSB typical; ensures monotonicity and accurate end-point linearity for closed-loop control feedback paths. |
| SNR | 80 dB typical at fIN = 500 kHz; delivers 13.0 effective number of bits (ENOB) for high-fidelity signal reconstruction. |
| Power Dissipation | 33 mW per channel at 2 Msps (CMOS mode, VDD = 5 V); reduces thermal load in dense PCB layouts. |
| Reference | Internal 4.096 V ±0.2% (or 2.048 V) with ≤20 ppm/°C drift; eliminates need for external precision reference and associated layout complexity. |
| Supply Range | VDD: 4.75 V to 5.25 V (5 V operation); OVDD: 1.71 V to 2.63 V; supports interoperability with 1.8 V/2.5 V FPGA I/O banks. |
Pinout & Package
Package: 28-lead (4 mm × 5 mm) plastic QFN (UFD) with exposed pad (Pin 29) soldered to ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (Pins 1, 8) | Analog power supply | Single 5 V rail powers both ADC cores and internal reference; requires local 10 µF + 0.1 µF bypassing. |
| AIN1+, AIN1– (Pins 7, 6) | Channel 1 differential analog input | Accepts ±4.096 V differential swing with 0 V to VDD common mode; no configuration needed for bipolar/unipolar modes. |
| AIN2+, AIN2– (Pins 2, 3) | Channel 2 differential analog input | Independent second channel with identical specs; enables simultaneous sampling for phase-sensitive applications. |
| CNV (Pin 9) | Conversion start trigger | Falling edge initiates hold-and-convert; must be driven by low-jitter source (<1 ps RMS jitter recommended). |
| SCK+, SCK– (Pins 21, 22) | Serial clock input | Differential LVDS or single-ended CMOS clock (up to 64 MHz); determines data readout timing and maximum throughput. |
| SDO1+, SDO1– (Pins 15, 16) | Channel 1 serial data output | MSB-first 15-bit two's complement code; LVDS mode requires 100 Ω differential termination at receiver. |
| CLKOUT+, CLKOUT– (Pins 17, 18) | Skew-matched output clock | Phase-aligned with SDO edges to eliminate setup/hold violations in FPGA-based capture logic. |
| REFOUT1, REFOUT2 (Pins 12, 26) | Reference buffer outputs | 4.096 V buffered references for each channel; decoupled locally with 10 µF + 0.1 µF ceramics (no vias). |
| REFINT (Pin 28) | Reference enable/disable | Tie to VDD for internal reference; ground to disable buffers and use external 1.25 V–5 V reference. |
| CMOS/LVDS (Pin 25) | I/O interface mode select | GND = CMOS; OVDD = LVDS; floating = low-power LVDS; configures driver strength and termination behavior. |
Key Features
| Feature | Design Value |
|---|---|
| No-cycle latency | Delivers first valid conversion result immediately after CNV falling edge-enables deterministic real-time control loop execution. |
| Dual independent SAR cores | Enables true simultaneous sampling of two signals (e.g., current/voltage in motor phase legs) without inter-channel timing skew. |
| Wide input common mode range (0 V to VDD) | Allows direct interface to op-amp outputs, isolated amplifiers, or sensor bridges without level-shifting circuitry. |
| Guaranteed no missing codes at 14 bits | Ensures monotonic transfer function across full temperature range (0°C to 70°C for LTC2321C grade), critical for position/speed encoders. |
| Low-power nap/sleep modes | Reduces total current to 5 µW in sleep mode-extends battery life in portable test equipment and remote DAQ nodes. |
Applications
| High-Speed Motor Control | Optical Network Monitoring |
|---|---|
|
Use Scenario: Real-time sampling of dual-phase current and bus voltage in servo drives operating at >20 kHz PWM frequencies. IC Role / Device Role / Timing Role: Dual-channel simultaneous ADC providing synchronized current/voltage feedback with <500 ps inter-channel matching for field-oriented control (FOC) algorithms. Use Value: Enables precise torque ripple suppression and dynamic response improvement by eliminating phase delay between current and voltage measurements. |
Use Scenario: Digitizing photodiode output and laser bias monitor signals in coherent optical transceivers for real-time power stabilization. IC Role / Device Role / Timing Role: High-SNR ADC capturing low-amplitude analog monitoring signals while rejecting switching noise from adjacent DC-DC converters. Use Value: 80 dB SNR and 85 dB CMRR ensure accurate detection of sub-mV signal variations amid high common-mode EMI in pluggable modules. |
| Industrial Data Acquisition | Automotive Battery Management |
|
Use Scenario: Multi-sensor acquisition (strain, temperature, vibration) in programmable logic controller (PLC) analog input modules requiring 14-bit resolution and long-term stability. IC Role / Device Role / Timing Role: Precision dual ADC with integrated 20 ppm/°C reference replacing external reference + dual ADC discrete solution. Use Value: Reduces BOM count by 3 components and improves system-level INL spec by eliminating reference mismatch between channels. |
Use Scenario: Cell voltage and pack current monitoring in 48 V mild-hybrid battery packs where space-constrained modules demand high integration. IC Role / Device Role / Timing Role: Dual ADC with 5 V supply compatibility and automotive-grade temp range (C-grade supports 0°C–70°C ambient). Use Value: Eliminates need for separate level-shifters when interfacing to 5 V microcontrollers and reduces thermal dissipation vs. older 16-bit sigma-delta alternatives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7960BCPZ-RL7 | 18-bit, 5 Msps, single-channel only; requires external reference and separate digital interface for dual-channel use. | Higher resolution but lacks native dual-channel synchronization; increases PCB area and timing complexity for multi-signal acquisition. | Select when absolute precision > speed, and system can accommodate discrete channel interleaving or dual IC layout. |
| ADS8864IDGSR | 16-bit, 1 Msps, single-supply 3 V only; no integrated reference; CMOS-only interface; smaller 10-pin VSSOP package. | Lower power (15 mW) but sacrifices 2× throughput and common-mode flexibility; unsuitable for 5 V systems or LVDS FPGA interfaces. | Select for ultra-low-power, space-constrained 3 V embedded systems where 1 Msps and external reference are acceptable trade-offs. |
Compared with AD7960BCPZ-RL7 and ADS8864IDGSR, the LTC2321CUFD-14#PBF uniquely delivers dual-channel 2 Msps operation with integrated reference and flexible 3.3 V/5 V/LVDS support-reducing design effort for time-critical industrial and automotive DAQ systems.
Availability
LTC2321CUFD-14#PBF is available at Aetrix Electronics and suitable for high-speed motor control, optical network monitoring, and industrial data acquisition requiring stable component supply across extended production lifecycles.
Supply support for LTC2321CUFD-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC2321 series was designed specifically for high-speed, high-accuracy data acquisition in space- and power-constrained systems-emphasizing dual-channel simultaneity, low-latency timing, and integrated reference stability without external components.
FAQ
What is the operating temperature range for the LTC2321CUFD-14#PBF?
The LTC2321CUFD-14#PBF is rated for 0°C to 70°C ambient operation (Commercial grade). This is confirmed by the "C" suffix in the part number and the Order Information table listing "0°C to 70°C" for LTC2321CUFD-14#PBF. It is not rated for industrial (–40°C to 85°C) or high-reliability (–40°C to 125°C) ranges.
Does the LTC2321CUFD-14#PBF support both CMOS and LVDS digital interfaces simultaneously?
No-the LTC2321CUFD-14#PBF supports either CMOS or LVDS mode, selected by the CMOS/LVDS pin (Pin 25): grounded for CMOS, tied to OVDD for LVDS, or floating for low-power LVDS. Both modes cannot operate concurrently; the interface type must be fixed at power-up.
Can the internal reference of the LTC2321CUFD-14#PBF be disabled to use an external reference?
Yes-driving REFINT (Pin 28) to GND disables both internal reference buffers (REFOUT1 and REFOUT2), allowing an external reference voltage from 1.25 V to 5 V to be applied directly to REFOUT1 and REFOUT2 pins. This is explicitly documented in the Pin Functions section and Electrical Characteristics table.
What is the maximum achievable throughput when using the LTC2321CUFD-14#PBF in LVDS mode?
The LTC2321CUFD-14#PBF maintains its full 2 Msps per channel throughput in LVDS mode. The ADC core timing (tCONV = 220 ns, tCYC = 500 ns minimum) is independent of interface mode; LVDS only affects the serial data transmission layer, not conversion rate.
Is the LTC2321CUFD-14#PBF pin-compatible with other variants in the LTC2321 family?
Yes-the LTC2321CUFD-14#PBF shares identical 28-lead QFN (UFD) packaging and pinout with LTC2321IUFD-14#PBF and LTC2321HUFD-14#PBF. All variants use the same mechanical footprint, thermal pad, and signal assignment; only temperature grade and screening differ.
LTC2321CUFD-14#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 2M
- Number of Inputs:
- 2
- Input Type:
- Differential, Pseudo-Differential
- Data Interface:
- LVDS - Serial, Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 3.13V ~ 3.47V, 5V
- Voltage - Supply, Digital:
- 3.13V ~ 3.47V, 5V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 28-QFN (4x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2321CUFD-14#PBF FAQ
1.How can I place an order for LTC2321CUFD-14#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2321CUFD-14#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2321CUFD-14#PBF reliable?
The price and inventory of LTC2321CUFD-14#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2321CUFD-14#PBF is usually 5 days.
3.What payment methods are accepted for LTC2321CUFD-14#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2321CUFD-14#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2321CUFD-14#PBF?
LTC2321CUFD-14#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2321CUFD-14#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2321CUFD-14#PBF?
For technical support, including LTC2321CUFD-14#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2321CUFD-14#PBF requirements.
6.How does Aetrix verify that LTC2321CUFD-14#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2321CUFD-14#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2321CUFD-14#PBF meets industry standards.
7.What is the process for return or replacement of LTC2321CUFD-14#PBF?
All LTC2321CUFD-14#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2321CUFD-14#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2321CUFD-14#PBF part is unused and in its original packaging.
Return procedure for LTC2321CUFD-14#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2321CUFD-14#PBF Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

