Analog Devices Inc. LTC2321CUFD-14#TRPBF
- Part No.:
- LTC2321CUFD-14#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC2321CUFD-14#TRPBF.pdf
- Description:
- IC ADC 14BIT SAR 28QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,435
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Product details
Overview
LTC2321CUFD-14#TRPBF from Analog Devices is a dual-channel, 14-bit + sign successive approximation register (SAR) analog-to-digital converter with differential inputs, 2 Msps per channel throughput, ±1 LSB typical INL, 80 dB SNR at 500 kHz, and integrated 2.048 V / 4.096 V temperature-compensated reference. It operates from single 3.3 V or 5 V supply and supports CMOS or LVDS serial interface for high-speed data acquisition in motor control and optical networking systems.
For engineers reviewing the LTC2321CUFD-14#TRPBF datasheet, LTC2321CUFD-14#TRPBF pinout, LTC2321CUFD-14#TRPBF application, or LTC2321CUFD-14#TRPBF equivalent, key selection criteria include no-cycle latency operation, guaranteed 14-bit no-missing-codes performance, wide input common mode range (0 V to VDD), 1.8 V–2.5 V I/O voltage compatibility, and support for both CMOS and LVDS signaling modes.
Technical Context
The LTC2321CUFD-14#TRPBF implements two independent SAR ADC cores with shared timing control, each featuring a 15-bit internal CDAC and differential comparator for precise successive approximation. Its acquisition phase connects 10 pF sampling capacitors via ~15 Ω switch RON to AIN+ and AIN–, enabling high-fidelity sampling of fully differential, pseudo-differential bipolar, or unipolar signals without configuration.
It integrates dual low-drift (≤20 ppm/°C) reference buffers delivering 4.096 V or 2.048 V, configurable via REFINT pin; supports internal reference or external reference up to 5 V. The SPI-compatible serial interface offers skew-matched CLKOUT for deterministic timing, with CMOS or LVDS mode selected by CMOS/LVDS pin state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit + sign (15-bit two's complement output), enabling ±32767 code range for full-scale differential input. |
| Sampling Rate | 2 Msps per channel, supporting real-time capture of signals up to 10 MHz linear bandwidth. |
| INL | ±1 LSB typical, ensuring monotonicity and <0.003% full-scale linearity error for precision measurement. |
| SNR | 80 dB typical at fIN = 500 kHz, corresponding to ~13.3 effective bits under standard test conditions. |
| Reference | Internal 4.096 V or 2.048 V buffer, max 20 ppm/°C drift, eliminating need for external precision reference in most applications. |
| Power | 33 mW per channel at 2 Msps (5 V supply, CMOS mode), dropping to 5 μW in sleep mode for power-sensitive systems. |
| Input Range | ±REFOUT differential (e.g., ±4.096 V), with 0 V to VDD common mode range - supports direct interfacing to op-amp outputs or sensor bridges without level-shifting. |
Pinout & Package
Package: 28-lead (4 mm × 5 mm) plastic QFN (UFD) with exposed pad (Pin 29) soldered to ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (1, 8) | Analog power supply | Single 3.3 V or 5 V supply for ADC core and reference buffers; requires local 10 µF + 0.1 µF bypassing. |
| AIN1+, AIN1− (6, 7); AIN2+, AIN2− (2, 3) | Differential analog inputs (Channel 1 & 2) | Accept ±REFOUT differential voltage; support fully differential, pseudo-differential bipolar/unipolar modes with no hardware configuration. |
| CNV (9) | Conversion start trigger | Falling edge initiates hold-and-convert sequence; requires low-jitter digital source synchronized to system clock domain. |
| SCK+, SCK− (21, 22) | Serial clock input | Differential LVDS or single-ended CMOS clock; falling edge shifts MSB-first conversion result onto SDO lines. |
| SDO1+, SDO1− / SDO2+, SDO2− (15,16 / 19,20) | Serial data outputs (Ch1 & Ch2) | LVDS-mode: differential outputs requiring 100 Ω termination; CMOS-mode: SDO+ active, SDO− unused. |
| CLKOUT+, CLKOUT− (17, 18) | Skew-matched output clock | Provides timing-aligned clock for latching SDO data at receiver; eliminates setup/hold uncertainty in FPGA/DSP interfaces. |
| REFOUT1, REFOUT2 (12, 26) | Reference buffer outputs | Nominally 4.096 V (or 2.048 V); decoupled with 0.1 µF + 10 µF ceramics; disable via REFINT = GND for external reference use. |
| CMOS/LVDS (25) | I/O interface mode select | GND = CMOS; OVDD = LVDS; floating = low-power LVDS - configures driver strength and termination behavior. |
Key Features
| Feature | Design Value |
|---|---|
| No-cycle latency | Eliminates pipeline delay between CNV edge and first valid data, enabling deterministic real-time control loop closure. |
| Wide input common mode range (0 V to VDD) | Allows direct connection to op-amps, current-sense amplifiers, or isolated signal conditioners without level-shifting circuitry. |
| Dual independent SAR cores with shared reference | Enables synchronous sampling of two channels with matched gain/offset, critical for phase-sensitive measurements like motor current sensing. |
| Configurable CMOS/LVDS I/O | Supports interoperability with legacy 1.8 V/2.5 V logic and high-noise immunity LVDS receivers in dense PCB layouts. |
| On-chip 2.048 V / 4.096 V reference with ≤20 ppm/°C drift | Reduces BOM count and layout area while maintaining ±0.008% full-scale accuracy over 0°C to 70°C operating range. |
Applications
| Motor Phase Current Sensing | Optical Network Monitoring |
|---|---|
|
Use Scenario: Real-time sampling of two motor phase currents in three-phase inverter drives for field-oriented control. IC Role / Device Role / Timing Role: Dual-channel simultaneous sampling ADC providing synchronized 14-bit + sign current measurements with no inter-channel skew. Use Value: Enables accurate torque estimation and fast overcurrent protection using native ±REFOUT differential input range and 2 Msps throughput. |
Use Scenario: Digitizing photodiode output voltages from multiple wavelength channels in DWDM transceivers. IC Role / Device Role / Timing Role: High-SNR ADC capturing low-amplitude optical monitoring signals with 80 dB SNR and 10 MHz linear bandwidth. Use Value: Supports precise power-level calibration and fault detection across C-band wavelengths without external amplification stages. |
| Industrial Data Acquisition | Automotive Battery Management |
|
Use Scenario: Multi-sensor data logging in programmable logic controller (PLC) analog input modules. IC Role / Device Role / Timing Role: Dual ADC converting isolated voltage/current sensor outputs with wide common mode rejection (85 dB CMRR). Use Value: Accepts inputs referenced to varying ground potentials (e.g., 4–20 mA loops) without signal conditioning, reducing component count. |
Use Scenario: Cell voltage monitoring in high-voltage EV battery packs with distributed sensing architecture. IC Role / Device Role / Timing Role: Precision ADC digitizing differential cell voltages across 100+ cells using isolated front-end amplifiers. Use Value: Internal 4.096 V reference ensures consistent full-scale scaling across modules; nap/sleep modes reduce quiescent current during idle periods. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7960BCPZ-RL7 | 18-bit, 5 Msps, single-channel only; requires external reference and separate clock generation; no LVDS option. | Higher resolution but lacks dual-channel synchronization and integrated reference; suited for lab-grade instrumentation, not real-time control. | Select when absolute precision > speed or channel count; avoid when simultaneous sampling or board space is constrained. |
| ADS8900BRGER | 16-bit, 1 Msps, single-supply 3.3 V only; CMOS-only interface; no internal reference; smaller 24-pin WQFN package. | Lower power (15 mW) and cost; limited to unipolar inputs; no common mode flexibility or LVDS noise immunity. | Select for portable or cost-sensitive designs where 14-bit resolution and dual-channel sync are unnecessary. |
Compared with AD7960BCPZ-RL7 and ADS8900BRGER, the LTC2321CUFD-14#TRPBF uniquely delivers dual-channel 14-bit + sign conversion with no-cycle latency, integrated reference, and LVDS/CMOS configurability - making it optimal for space-constrained, noise-sensitive real-time control systems requiring synchronized sampling.
Availability
LTC2321CUFD-14#TRPBF is available at Aetrix Electronics and suitable for high-speed data acquisition systems, optical networking equipment, and multiphase motor control applications requiring stable component supply, extended temperature reliability, and long-term production continuity.
Supply support for LTC2321CUFD-14#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC2321CUFD-14#TRPBF belongs to the Linear Technology high-speed precision ADC product line, designed specifically for demanding real-time control and instrumentation applications requiring low latency, high SNR, and flexible analog input architectures.
FAQ
What is the operating temperature range for the LTC2321CUFD-14#TRPBF?
The LTC2321CUFD-14#TRPBF is rated for 0°C to 70°C ambient operation (C-grade). This is confirmed in the Order Information table, where "LTC2321CUFD-14#TRPBF" is explicitly listed with "0°C to 70°C" temperature range. It uses the same UFD QFN package and internal design as the I- and H-grade variants but is characterized and screened for commercial temperature performance only.
Does the LTC2321CUFD-14#TRPBF support both CMOS and LVDS digital interfaces?
Yes, the LTC2321CUFD-14#TRPBF supports both CMOS and LVDS serial interfaces. Pin 25 (CMOS/LVDS) selects the mode: grounded for CMOS, tied to OVDD for LVDS, or left floating for low-power LVDS. Both SDO and CLKOUT pins operate differentially in LVDS mode with 100 Ω termination, while CMOS mode uses single-ended SDO+/CLKOUT+ outputs referenced to OVDD (1.8 V or 2.5 V).
What reference voltage options does the LTC2321CUFD-14#TRPBF provide internally?
The LTC2321CUFD-14#TRPBF provides two internal reference voltage options: nominally 2.048 V or 4.096 V, selectable via the REFINT pin configuration and supply voltage (VDD = 3.3 V or 5 V). The reference buffers exhibit ≤20 ppm/°C temperature drift and are decoupled via dedicated REFOUT1/REFOUT2 and REFRTN1/REFRTN2 pins with recommended 0.1 µF + 10 µF ceramic capacitors.
How does the LTC2321CUFD-14#TRPBF handle pseudo-differential input configurations?
The LTC2321CUFD-14#TRPBF natively supports pseudo-differential bipolar and unipolar inputs without hardware configuration. For pseudo-differential bipolar, one input (e.g., AIN1−) is held at a fixed voltage (e.g., VREF/2) while the signal drives AIN1+ - yielding ±REFOUT/2 span and symmetric two's complement codes. For unipolar, AIN1− is grounded and AIN1+ accepts 0 V to REFOUT, producing 0 to +REFOUT range with 14-bit resolution.
What power-saving modes does the LTC2321CUFD-14#TRPBF offer?
The LTC2321CUFD-14#TRPBF offers Nap and Sleep modes. In Nap mode (conversion complete), power drops to 7.8–13 mW depending on supply and interface mode. In Sleep mode (fully idle), total current falls to 1–5 µA, dissipating just 5–25 µW - verified in the Power Requirements table under "Sleep Mode" rows for both 3.3 V and 5 V operation with CMOS/LVDS configurations.
LTC2321CUFD-14#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 2M
- Number of Inputs:
- 2
- Input Type:
- Differential, Pseudo-Differential
- Data Interface:
- LVDS - Serial, Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- SAR
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 3.13V ~ 3.47V, 5V
- Voltage - Supply, Digital:
- 3.13V ~ 3.47V, 5V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 28-QFN (4x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2321CUFD-14#TRPBF FAQ
1.How can I place an order for LTC2321CUFD-14#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2321CUFD-14#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2321CUFD-14#TRPBF reliable?
The price and inventory of LTC2321CUFD-14#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2321CUFD-14#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2321CUFD-14#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2321CUFD-14#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2321CUFD-14#TRPBF?
LTC2321CUFD-14#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2321CUFD-14#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2321CUFD-14#TRPBF?
For technical support, including LTC2321CUFD-14#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2321CUFD-14#TRPBF requirements.
6.How does Aetrix verify that LTC2321CUFD-14#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2321CUFD-14#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2321CUFD-14#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2321CUFD-14#TRPBF?
All LTC2321CUFD-14#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2321CUFD-14#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2321CUFD-14#TRPBF part is unused and in its original packaging.
Return procedure for LTC2321CUFD-14#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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