Analog Devices Inc. LTC2325CUKG-12#PBF

Overview

LTC2325CUKG-12#PBF from Analog Devices is a quad-channel, 12-bit + sign successive approximation register (SAR) analog-to-digital converter with simultaneous sampling, 5 Msps per channel throughput, ±0.5 LSB typical INL, 77 dB SNR at 2.2 MHz input, and integrated 4.096 V temperature-compensated reference - designed for high-speed data acquisition in multiphase motor control and optical networking systems.

For engineers reviewing the LTC2325CUKG-12#PBF datasheet, LTC2325CUKG-12#PBF pinout, LTC2325CUKG-12#PBF application, or LTC2325CUKG-12#PBF equivalent, this page delivers verified electrical specs, validated QFN-52 pin functions, real-world timing behavior across CMOS/LVDS modes, and direct alternative part comparisons for precision ADC selection.

Technical Context

The LTC2325CUKG-12#PBF implements four independent SAR ADC cores sharing a common reference architecture with individually buffered REFOUT1–4 outputs. Each channel features true differential inputs with ±4.096 V full-scale range, 95 MHz –3 dB input bandwidth, and aperture jitter of 1 ps RMS - enabling coherent sampling across all four channels without external synchronization.

Its dual-mode serial interface supports CMOS (1.8 V/2.5 V I/O) or LVDS (2.5 V OVDD) operation with selectable SDR/DDR clocking, and includes dedicated CLKOUT with skew-matched delay for FPGA capture. Power management includes nap mode (6.4 mA) and sleep mode (20 µA), with total dissipation of 162 mW at 5 V/5 Msps.

Key Specifications

Pinout & Package

Package: 52-lead (7 mm × 8 mm) plastic QFN with exposed thermal pad (Pin 53 = GND). RoHS-compliant, lead-free finish (PBF).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-channel, high-speed SAR ADC applications.

Compared with AD7606C-16 and ADS8684, the LTC2325CUKG-12#PBF uniquely combines 5 Msps simultaneous sampling, LVDS/CMOS flexibility, and integrated 4.096 V reference in a single QFN package - making it optimal for FPGA-based real-time control and broadband signal analysis where timing coherence and interface robustness are non-negotiable.

Availability

LTC2325CUKG-12#PBF is available at Aetrix Electronics and suitable for high-speed data acquisition systems, optical network test equipment, and multiphase motor control applications requiring stable component supply, long-term lifecycle support, and guaranteed C-grade (0°C to 70°C) performance.

Supply support for LTC2325CUKG-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.

The LTC2325 series belongs to Analog Devices' high-speed precision SAR ADC product line, engineered specifically for applications demanding simultaneous multi-channel sampling, low-latency digital interfaces, and integrated reference stability - such as real-time motor control and optical signal analysis.

FAQ

What is the maximum sampling rate per channel for the LTC2325CUKG-12#PBF?

The LTC2325CUKG-12#PBF achieves a maximum sampling rate of 5 Msps per channel, with guaranteed timing across all four simultaneously sampled channels. This rate is supported in both CMOS and LVDS interface modes, with conversion time fixed at 170 ns and one-cycle latency - enabling deterministic real-time data capture for FPGA-based processing pipelines.

Does the LTC2325CUKG-12#PBF require an external reference voltage?

No, the LTC2325CUKG-12#PBF includes an onboard low-drift 4.096 V temperature-compensated reference with ≤20 ppm/°C drift, eliminating the need for external references in most applications. The REFBUFEN pin allows disabling internal buffers if an external reference (1.25 V to 5 V) is preferred - but the LTC2325CUKG-12#PBF operates fully functional with its internal reference enabled.

How does the CMOS/LVDS pin affect interface configuration on the LTC2325CUKG-12#PBF?

The CMOS/LVDS pin (Pin 25) selects the digital I/O standard: grounding it enables CMOS mode (1.8 V/2.5 V logic), tying it to OVDD enables LVDS mode (2.5 V differential), and leaving it floating activates low-power LVDS. This setting determines driver topology, termination requirements, and power consumption - and must match the host FPGA's I/O bank configuration to ensure signal integrity at up to 105 MHz SCK rates.

Can the LTC2325CUKG-12#PBF operate with a 3.3 V supply instead of 5 V?

Yes, the LTC2325CUKG-12#PBF is fully specified for operation from either a 3.3 V or 5 V VDD supply. At 3.3 V, typical power dissipation drops to 102 mW (active), 18 mW (nap), and 20 µW (sleep), while maintaining full 12-bit + sign resolution, 5 Msps throughput, and 77 dB SNR - making it suitable for portable or thermally constrained industrial systems.

What is the purpose of the SDR/DDR pin on the LTC2325CUKG-12#PBF?

The SDR/DDR pin (Pin 23) controls serial data clocking mode: tied to GND for Single Data Rate (SDR), where data shifts on SCK falling edges only; tied to OVDD for Double Data Rate (DDR), where data shifts on both SCK edges. DDR reduces required SCK frequency by 2× for the same data throughput - e.g., 52.5 MHz SCK instead of 105 MHz - easing timing closure in high-speed FPGA designs using the LTC2325CUKG-12#PBF.