Analog Devices Inc. LTC2351IUH-12#PBF
- Part No.:
- LTC2351IUH-12#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LTC2351IUH-12#PBF.pdf
- Description:
- IC ADC 12BIT 32QFN
- Quantity:
- Payment:

- Shipping:

Inventory:460
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Product details
Overview
LTC2351IUH-12#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 1.5 Msps simultaneous-sampling ADC with six differential input channels, 72 dB SINAD, 83 dB common-mode rejection, and operation from a single 3 V supply. It delivers 250 ksps per channel throughput in a 32-pin 5 mm × 5 mm QFN package, targeting high-precision multiphase power measurement and motor control systems.
For engineers reviewing the LTC2351IUH-12#PBF datasheet, LTC2351IUH-12#PBF pinout, LTC2351IUH-12#PBF application, or LTC2351IUH-12#PBF equivalent, key selection criteria include simultaneous sampling integrity, bipolar/unipolar mode flexibility via BIP pin, low-power Nap/Sleep modes (4.5 mW / 12 μW), SPI-compatible serial interface timing, and rail-to-rail analog input compliance under ±1.25 V or 0–2.5 V differential ranges.
Technical Context
The LTC2351IUH-12#PBF integrates six independent sample-and-hold circuits triggered synchronously on the rising edge of CONV, enabling true simultaneous acquisition across all channels. Conversion proceeds at 250 ksps per channel using a 12-bit successive-approximation architecture with internal 2.5 V bandgap reference (±15 ppm/°C tempco).
Its 3-wire SPI-compatible serial interface outputs six 12-bit words in 96 SCK cycles, supporting channel-selectable conversion sequences (1–6 channels) via SEL2/SEL1/SEL0. The device supports two shutdown states-Nap (4.5 mW) and Sleep (12 μW)-activated by repeated CONV pulses without clock activity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes; guarantees monotonic transfer function for precision control loop feedback. |
| Sampling Rate | 1.5 Msps aggregate (250 ksps per channel); enables real-time capture of fast transients across all six phases. |
| SINAD | 72 dB at 100 kHz input; ensures ≥11.6 effective bits for accurate RMS and harmonic analysis in power quality monitoring. |
| Common-Mode Rejection | 83 dB at 100 kHz; eliminates ground-loop-induced errors in noisy industrial environments with distributed sensors. |
| Power Consumption | 16.5 mW active, 4.5 mW Nap, 12 μW Sleep; allows battery-backed data loggers to extend runtime without sacrificing sampling fidelity. |
| Analog Input Range | 0 V to 2.5 V unipolar or ±1.25 V bipolar (BIP pin controlled); supports both DC-biased and AC-coupled sensor interfaces without external level-shifting. |
| Channel-to-Channel Skew | 200 ps aperture skew; preserves phase coherence between voltage/current measurements in multiphase inverters. |
Pinout & Package
Package: 32-pin plastic QFN (5 mm × 5 mm), exposed pad (Pin 33) soldered to PCB ground for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CH0+ to CH5+ | Non-inverting analog inputs (6 pairs) | Differential signal acquisition points; each pair must be driven within 0 V to VDD absolute range and maintains 83 dB CMRR. |
| CH0– to CH5– | Inverting analog inputs (6 pairs) | Completes differential pair; full rail-to-rail swing allowed as long as differential voltage stays within ±1.25 V or 0–2.5 V range. |
| CONV (Pin 30) | Conversion start trigger | Rising-edge–synchronized simultaneous sampling; also controls Nap/Sleep entry via pulse count without SCK activity. |
| SCK (Pin 32) | Serial clock input | Drives 96-cycle readout sequence; minimum 40 ns period ensures full dynamic performance compliance. |
| SDO (Pin 1) | Three-state serial data output | MSB-first output of six 12-bit words; Hi-Z state enabled when SCK inactive, simplifying bus sharing in multi-device systems. |
| BIP (Pin 29) | Bipolar/unipolar mode select | Static logic level sets output coding (2's complement or straight binary) and input range; requires full tACQ (39 ns) before next CONV if changed. |
| SEL2/SEL1/SEL0 (Pins 26–28) | Channel count selector | 3-bit code defines number of converted channels (1–6); determines total SCK cycles (16–96) and per-channel throughput (500 ksps down to 250 ksps). |
| VREF (Pin 23) | Internal 2.5 V reference output | Stable 2.5 V ±15 ppm/°C source; bypassed with 10 μF + 0.1 μF for <2 ms wake-up settling after Sleep mode. |
Key Features
| Feature | Design Value |
|---|---|
| Simultaneous sampling | Six independent S/H circuits triggered by single CONV edge ensure phase-aligned acquisition for vector control and power factor calculation. |
| Configurable channel count | SEL2/SEL1/SEL0 pins allow dynamic reduction of active channels (e.g., 3-channel mode → 500 ksps/ch), optimizing latency vs. channel density trade-offs. |
| Dual-range analog input | BIP pin selects 0–2.5 V unipolar (straight binary) or ±1.25 V bipolar (2's complement) input ranges, eliminating external gain/level-shift circuitry. |
| Low-power shutdown modes | Nap (4.5 mW) and Sleep (12 μW) reduce idle power by >99.9% while retaining register state and enabling sub-microsecond wake-up via SCK or CONV. |
| High CMRR & low skew | 83 dB CMRR at 100 kHz and 200 ps channel-to-channel aperture skew preserve signal integrity in EMI-heavy motor drive and grid-tie inverter applications. |
Applications
| Multiphase Power Measurement | Multiphase Motor Control |
|---|---|
Use Scenario: Real-time monitoring of line-to-line voltages and phase currents in 3-phase AC distribution panels or UPS systems. IC Role / Device Role / Timing Role: Simultaneous sampling ADC capturing six synchronized analog inputs for RMS, THD, and power factor computation. Use Value: 200 ps channel skew and 83 dB CMRR prevent phase error accumulation in digital energy metering algorithms. |
Use Scenario: Closed-loop field-oriented control (FOC) of PMSM or induction motors using back-EMF and current feedback. IC Role / Device Role / Timing Role: Six-channel synchronous acquisition of motor phase currents and DC-link voltage for torque ripple minimization. Use Value: 250 ksps/ch throughput and 72 dB SINAD enable accurate current reconstruction up to 125 kHz bandwidth for high-speed servo drives. |
| Data Acquisition Systems | Uninterruptible Power Supplies |
Use Scenario: Modular industrial DAQ modules requiring high channel density, low power, and deterministic sampling in compact enclosures. IC Role / Device Role / Timing Role: Core ADC engine with configurable channel count and SPI interface for FPGA- or MCU-based system integration. Use Value: 5 mm × 5 mm QFN package and 16.5 mW active power allow dense channel packing without thermal derating. |
Use Scenario: Input/output voltage/current monitoring and battery health assessment in online double-conversion UPS units. IC Role / Device Role / Timing Role: Simultaneous capture of AC input, DC bus, and battery terminals during transfer switching events. Use Value: Sleep mode (12 μW) enables always-on monitoring during standby with minimal impact on backup runtime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar simultaneous-sampling ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8686SIPWR | 16-bit, 1 MSPS, 6-channel SAR ADC; integrated programmable gain amplifier (PGA); 3.3 V supply only; no Sleep mode. | Higher resolution for precision metrology; PGA enables direct connection to mV-level sensors; lacks ultra-low-power Sleep mode. | Select when resolution >12-bit and sensor-level gain are required; avoid when battery life or thermal constraints demand <12 μW idle power. |
| AD7606C-16BSTZ | 16-bit, 1 MSPS, 8-channel simultaneous-sampling ADC; ±5 V/±10 V input ranges; 2.5 V internal reference; 120 mW active power. | Wider input voltage range suits industrial PLC analog I/O; higher power and larger LQFP package limit portable use. | Select for ±10 V sensor interfacing and legacy 5 V system compatibility; avoid when 3 V operation, QFN footprint, or sub-20 mW power are mandatory. |
Compared with ADS8686SIPWR and AD7606C-16BSTZ, the LTC2351IUH-12#PBF offers the lowest active and sleep power in a compact QFN, optimized for 3 V battery-powered or thermally constrained multiphase sensing - trading resolution for efficiency and integration density.
Availability
LTC2351IUH-12#PBF is available at Aetrix Electronics and suitable for multiphase power measurement, motor control, and uninterruptible power supply applications requiring stable component supply, guaranteed temperature range (–40°C to +85°C), and long-term production continuity.
Supply support for LTC2351IUH-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2351IUH-12#PBF belongs to ADI's precision data acquisition portfolio, designed specifically for space- and power-constrained systems needing synchronized multichannel sampling - such as energy meters, servo drives, and portable test equipment.
FAQ
What is the operating temperature range of the LTC2351IUH-12#PBF?
The LTC2351IUH-12#PBF is rated for –40°C to +85°C ambient operation, matching the "I" grade specification. This extended industrial temperature range ensures reliable performance in motor control cabinets, outdoor power converters, and factory-floor data loggers where thermal cycling occurs.
How does the BIP pin affect output data format and input range in the LTC2351IUH-12#PBF?
When BIP = LOW, the LTC2351IUH-12#PBF accepts 0 V to 2.5 V differential inputs and outputs straight binary codes. When BIP = HIGH, it accepts ±1.25 V differential inputs and outputs 2's complement codes. The BIP state must remain static during conversion and readout; changing it requires full 39 ns acquisition time before the next CONV pulse.
Can the LTC2351IUH-12#PBF convert fewer than six channels, and how is this configured?
Yes - the LTC2351IUH-12#PBF supports 1–6 channel conversion via SEL2/SEL1/SEL0. For example, SEL2=0, SEL1=0, SEL0=1 configures 2-channel mode (CH0 and CH1), reducing total conversion time from 96 to 32 SCK cycles and increasing per-channel throughput to 500 ksps. All SEL pins must remain static during conversion and readout.
What are the power states of the LTC2351IUH-12#PBF, and how are they entered?
The LTC2351IUH-12#PBF has three power states: Active (16.5 mW), Nap (4.5 mW), and Sleep (12 μW). Nap is entered with two CONV pulses while SCK is held static; Sleep requires four or more such pulses. Both modes retain configuration and resume full operation within microseconds upon first SCK or CONV edge.
Does the LTC2351IUH-12#PBF require an external reference, or is the internal reference sufficient?
The LTC2351IUH-12#PBF includes a 2.5 V internal bandgap reference with ±15 ppm/°C tempco and 2 ms settling time after Sleep wake-up. It is fully functional without external components but can be overdriven by a precision external reference (2.55 V to VDD) for improved accuracy in metrology-grade applications.
LTC2351IUH-12#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 1.5M
- Number of Inputs:
- 6
- Input Type:
- Differential, Pseudo-Differential
- Data Interface:
- SPI
- Configuration:
- S/H-MUX-ADC
- Ratio - S/H:ADC:
- 6:1
- Number of A/D Converters:
- 1
- Architecture:
- -
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.6V
- Voltage - Supply, Digital:
- 2.7V ~ 3.6V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-QFN (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2351IUH-12#PBF FAQ
1.How can I place an order for LTC2351IUH-12#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2351IUH-12#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2351IUH-12#PBF reliable?
The price and inventory of LTC2351IUH-12#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2351IUH-12#PBF is usually 5 days.
3.What payment methods are accepted for LTC2351IUH-12#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2351IUH-12#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2351IUH-12#PBF?
LTC2351IUH-12#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2351IUH-12#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2351IUH-12#PBF?
For technical support, including LTC2351IUH-12#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2351IUH-12#PBF requirements.
6.How does Aetrix verify that LTC2351IUH-12#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2351IUH-12#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2351IUH-12#PBF meets industry standards.
7.What is the process for return or replacement of LTC2351IUH-12#PBF?
All LTC2351IUH-12#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2351IUH-12#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2351IUH-12#PBF part is unused and in its original packaging.
Return procedure for LTC2351IUH-12#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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