Analog Devices Inc. LTC2356CMSE-12#PBF

Overview

LTC2356CMSE-12#PBF from Analog Devices (formerly Linear Technology) is a 12-bit, 3.5 Msps serial analog-to-digital converter with differential inputs, single 3.3 V supply operation, ±1.25 V bipolar input range, and 71.1 dB SINAD at 100 kHz. It delivers high-speed data acquisition in portable instrumentation and multiplexed sensor systems.

For engineers reviewing the LTC2356CMSE-12#PBF datasheet, LTC2356CMSE-12#PBF pinout, LTC2356CMSE-12#PBF application, or LTC2356CMSE-12#PBF equivalent, key selection criteria include sampling rate vs. power trade-off (18 mW active), differential CMRR (80 dB), SPI-compatible 3-wire interface timing, and MSOP-10 package thermal performance with exposed pad grounding.

Technical Context

The LTC2356CMSE-12#PBF implements a fully differential sample-and-hold architecture with 39 ns acquisition time and 1 ns aperture delay jitter (0.3 ps typical), enabling accurate high-frequency signal capture. Its internal 2.5 V bandgap reference supports ±1.25 V input span and can be overdriven by an external 2.55 V to 3.3 V reference.

Conversion is triggered on the rising edge of CONV; output data appears on SDO over 16 clock cycles following that edge. Full 3.5 Msps throughput requires 63 MHz SCK with two extra clock cycles between conversions for acquisition recovery.

Key Specifications

Pinout & Package

Package: 10-lead plastic MSOP with exposed thermal pad (Pin 11), rated for 0°C to 70°C operation. Exposed pad must be soldered to PCB ground plane for thermal and noise performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed SAR ADC applications.

Compared with ADS8860IRGET and MAX11198ETE+, the LTC2356CMSE-12#PBF uniquely balances 3.5 Msps throughput, 13 µW Sleep power, and 80 dB CMRR in a thermally optimized MSOP-10 - making it optimal for portable, noise-sensitive, high-sample-rate systems where power budget and layout density are co-constrained.

Availability

LTC2356CMSE-12#PBF is available at Aetrix Electronics and suitable for portable data loggers, multiphase motor control systems, and uninterruptible power supplies requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LTC2356CMSE-12#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2356 family was designed for high-speed, low-power, differential data acquisition in space- and power-constrained embedded systems - emphasizing integration, noise immunity, and ease of use in single-supply environments.

FAQ

What is the absolute maximum input voltage range for LTC2356CMSE-12#PBF analog inputs?

The absolute voltage at AIN+ and AIN– must remain within –0.3 V to (VDD + 0.3 V), per Absolute Maximum Ratings. With VDD = 3.3 V, this means –0.3 V to 3.6 V. The differential input range is limited to ±1.25 V, but common-mode voltage may extend from ground to VDD. Exceeding these limits risks latch-up or permanent damage.

Does LTC2356CMSE-12#PBF require an external reference, or does it have an internal one?

LTC2356CMSE-12#PBF includes a factory-trimmed 2.5 V internal bandgap reference (Pin 3, VREF) that supports its ±1.25 V input range. This reference can be overdriven by an external 2.55 V to 3.3 V source if higher accuracy or different span is needed. No external reference is required for basic operation.

How does the Sleep mode of LTC2356CMSE-12#PBF work, and what is its wake-up time?

Sleep mode is entered after four or more CONV pulses with SCK held static (high or low). Power drops to 13 µW. Wake-up occurs on the first SCK edge, and the internal reference settles in 2 ms (with 10 µF bypass cap), after which valid conversions resume. LTC2356CMSE-12#PBF maintains full specification compliance post-wake.

Can LTC2356CMSE-12#PBF interface directly with an FPGA without level-shifting?

Yes. LTC2356CMSE-12#PBF digital I/Os (SCK, CONV, SDO) operate at 3.3 V CMOS/TTL levels: VIH = 2.4 V min, VOL = 0.1 V max at 160 µA. When interfaced with 3.3 V FPGA I/O banks configured for LVCMOS33, no level-shifting is needed. Ensure proper decoupling and controlled impedance routing for SCK/SDO timing integrity.

What is the minimum acquisition time for LTC2356CMSE-12#PBF, and how does source impedance affect it?

The guaranteed acquisition time for LTC2356CMSE-12#PBF is 39 ns under nominal conditions (low source impedance). As source impedance increases, acquisition time lengthens due to RC time constant with 13 pF input capacitance. For high-impedance sources (>100 Ω), a buffer amplifier with ≥40 MHz closed-loop bandwidth and <100 Ω output impedance is required to maintain full 3.5 Msps throughput.