Analog Devices Inc. LTC2364CDE-18#TRPBF
- Part No.:
- LTC2364CDE-18#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 16-WFDFN Exposed Pad
- Datasheet:
-
LTC2364CDE-18#TRPBF.pdf
- Description:
- IC ADC 18BIT SAR 16DFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,912
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2364CDE-18#TRPBF from Analog Devices (formerly Linear Technology) is an 18-bit, 250ksps pseudo-differential unipolar successive approximation register (SAR) ADC operating from a single 2.5V supply. It delivers 97dB SNR (typ), ±2.5LSB INL (max), no missing codes at 18 bits, and supports VREF from 2.5V to 5.1V - enabling high-precision data acquisition in compact, low-power instrumentation.
For engineers reviewing the LTC2364CDE-18#TRPBF datasheet, LTC2364CDE-18#TRPBF pinout, LTC2364CDE-18#TRPBF application, or LTC2364CDE-18#TRPBF equivalent, key selection criteria include guaranteed 18-bit no-missing-codes performance, daisy-chain SPI interface compatibility with 1.8V–5V logic, internal conversion clock, and operation across 0°C to 70°C in the 4mm × 3mm DFN package.
Technical Context
The LTC2364CDE-18#TRPBF implements a charge-redistribution CDAC architecture with pseudo-differential sampling, where IN+ accepts 0V to VREF input while IN– serves as ground-sense reference (±100mV range). Conversion is initiated by a rising edge on CNV, with no pipeline delay and fixed 1.9–3µs conversion time set by an internal oscillator.
Its SPI-compatible serial interface supports both normal mode (RDL/SDI as bus enable) and daisy-chain mode (RDL/SDI as SDI when CHAIN = HIGH), with SDO outputting straight-binary 18-bit data MSB-first on SCK rising edges. Power scales dynamically: 3.4mW at 250ksps, dropping to 3.4µW at 250sps via automatic power-down between conversions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 18-bit - guarantees full 262,144 quantization levels with no missing codes across temperature. |
| Sampling Rate | 250ksps - enables real-time capture of signals up to 125kHz Nyquist bandwidth without undersampling. |
| SNR | 97dB (typ, fIN = 2kHz, VREF = 5V) - supports >15.8 effective number of bits (ENOB) for high-fidelity signal digitization. |
| INL | ±2.5LSB (max) - ensures monotonicity and linearity critical for closed-loop control and calibration-sensitive systems. |
| Power Consumption | 3.4mW at 250ksps - allows battery-powered operation with minimal thermal impact in space-constrained layouts. |
| Reference Range | VREF = 2.5V to 5.1V - permits flexible scaling from low-voltage sensor outputs to full-scale industrial signals. |
| Supply Voltages | VDD = 2.375V–2.625V; OVDD = 1.71V–5.25V - decouples analog core from digital I/O, enabling interoperability with mixed-voltage host systems. |
Pinout & Package
Package: 16-lead (4mm × 3mm) plastic DFN with exposed pad (Pin 17), rated for 0°C to 70°C operation. Exposed pad must be soldered to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CHAIN (1) | Mode selector | High enables daisy-chain SPI mode (RDL/SDI becomes SDI); low enables normal mode (RDL/SDI acts as bus enable). |
| VDD (2) | Analog core supply | 2.5V ±62.5mV supply for SAR core; bypass with 10µF ceramic capacitor to GND. |
| GND (3,6,10,16) | Analog/digital ground | Multiple ground pins minimize impedance; Pin 17 (exposed pad) is dedicated GND for DFN thermal path. |
| IN+ (4) | Pseudo-differential input (+) | Accepts 0V to VREF input; sees 45pF capacitance and 40Ω switch resistance during acquisition. |
| IN– (5) | Pseudo-differential input (–) | Ground-sense reference with ±100mV range; must connect to system ground or remote ground plane. |
| REF (7,8) | Reference voltage input | Dual-pin connection for 2.5V–5.1V external reference; requires 47µF X5R ceramic decoupling at pin. |
| CNV (9) | Convert trigger | Rising-edge–initiated conversion start; powers up ADC and begins acquisition phase. |
| BUSY (11) | Conversion status indicator | Active-high open-drain output signaling conversion in progress; synchronized to CNV timing. |
| RDL/SDI (12) | Serial data control/input | Function depends on CHAIN state: bus enable (low) or serial data input (high) for daisy-chain cascading. |
| SCK (13) | Serial clock input | Drives data transfer timing; supports up to 100MHz SCK frequency with 10ns min period. |
| SDO (14) | Serial data output | MSB-first straight-binary 18-bit output; valid after tDSDO (9.5ns) from SCK↑ with CL = 20pF. |
| OVDD (15) | I/O interface supply | 1.71V–5.25V logic supply; sets VIH/VIL thresholds and powers SDO/BUSY/RDL/SDI/SCK buffers. |
Key Features
| Feature | Design Value |
|---|---|
| No cycle latency | Immediate data availability after BUSY goes low - eliminates FIFO buffering and simplifies real-time control loop timing. |
| Daisy-chain SPI mode | Enables multi-ADC synchronization with single SCK/SDO line - reduces PCB routing complexity and host GPIO count. |
| Internal conversion clock | Removes need for external timing circuitry - improves system reliability and reduces BOM cost and layout area. |
| Auto power-down | Reduces current to 0.9µA (typ) between conversions - extends battery life in intermittent-sampling applications. |
| Pseudo-differential architecture | Rejects common-mode noise on IN+/IN– pair - enhances immunity in noisy industrial environments without requiring matched drivers. |
| 1.8V–5V I/O compatibility | Interoperates with legacy 5V microcontrollers and modern 1.8V FPGAs without level shifters - accelerates integration. |
Applications
| Medical Imaging Signal Chain | Portable High-Speed Data Logger |
|---|---|
Use Scenario: Digitizing low-amplitude, high-frequency ultrasound echo signals in handheld imaging probes. IC Role / Device Role / Timing Role: Primary SAR ADC capturing 250ksps RF envelope data with <1.3LSB RMS noise floor. Use Value: 97dB SNR preserves weak tissue boundary reflections; 18-bit resolution enables precise dynamic range compression for grayscale rendering. |
Use Scenario: Battery-powered environmental monitoring node recording vibration, temperature, and acoustic emissions over extended periods. IC Role / Device Role / Timing Role: Low-power precision ADC sampling sensor outputs at adaptive rates (250ksps burst or 250sps sleep). Use Value: 3.4µW standby power extends 10-year battery life; daisy-chain mode allows multi-channel expansion without added MCU pins. |
| Industrial Process Controller ADC | ATE Front-End Digitizer |
Use Scenario: Closed-loop feedback in servo drives measuring motor current and position encoder signals under EMI-heavy factory conditions. IC Role / Device Role / Timing Role: High-linearity ADC interfacing with isolated current shunt amplifiers and resolver-to-digital converters. Use Value: ±2.5LSB INL ensures sub-0.01% gain error stability; pseudo-differential inputs reject common-mode noise from switching power supplies. |
Use Scenario: Automated test equipment capturing transient waveforms from DUTs during functional validation and parametric testing. IC Role / Device Role / Timing Role: Precision digitizer synchronizing with pattern generators and digital I/O via CNV-triggered acquisition. Use Value: No pipeline latency enables deterministic sample alignment; 250ksps throughput supports 100+ channel multiplexing at 2.5ksps/channel. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7986BCPZ-RL7 | 18-bit, 1MSPS, but requires external reference and separate VIO supply; higher 12.5mW power at full rate. | Higher speed suits broadband spectrum analysis; less suitable for ultra-low-power portable use. | Select when >250ksps throughput is mandatory and board space allows larger decoupling network. |
| ADS8860IRGET | 16-bit, 1MSPS, SPI-only interface (no daisy-chain), 2.5V–5V VIO, 3.3mW at 100ksps. | Limited to 16-bit resolution; lacks guaranteed no-missing-codes spec and pseudo-differential input flexibility. | Choose for cost-sensitive, lower-resolution applications where 16-bit ENOB suffices and daisy-chain is unnecessary. |
Compared with AD7986BCPZ-RL7 and ADS8860IRGET, the LTC2364CDE-18#TRPBF uniquely balances 18-bit integrity, 250ksps speed, ultra-low 3.4mW power, and integrated daisy-chain capability - making it optimal for space- and energy-constrained multi-channel systems requiring metrology-grade linearity.
Availability
LTC2364CDE-18#TRPBF is available at Aetrix Electronics and suitable for medical imaging signal chains, portable high-speed data loggers, and industrial process controllers requiring stable component supply with traceable sourcing and long-term lifecycle support.
Supply support for LTC2364CDE-18#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2364-18 product line was designed for high-accuracy, low-power data acquisition in space-constrained and thermally sensitive applications - emphasizing no-missing-codes assurance, internal timing autonomy, and flexible I/O voltage compatibility.
FAQ
What is the maximum recommended reference voltage for the LTC2364CDE-18#TRPBF?
The LTC2364CDE-18#TRPBF supports VREF from 2.5V to 5.1V per absolute maximum ratings and electrical specifications. Operation at 5.1V maximizes input dynamic range and LSB size (19.4µV), but requires careful attention to REF pin current (up to 0.2mA at 250ksps) and decoupling (47µF X5R ceramic capacitor). Exceeding 5.1V risks permanent damage.
Does the LTC2364CDE-18#TRPBF require external clocking for conversion timing?
No - the LTC2364CDE-18#TRPBF features an internal oscillator that sets conversion time (1.9–3µs), eliminating dependency on external clocks. The only required timing signal is the CNV pulse to initiate acquisition. This simplifies system design and improves jitter immunity compared to externally clocked SAR ADCs.
How does the pseudo-differential input architecture of the LTC2364CDE-18#TRPBF improve noise rejection?
The LTC2364CDE-18#TRPBF's pseudo-differential input uses IN+ (0V to VREF) and IN– (±100mV around GND) to reject common-mode noise. With 80dB CMRR at 125kHz, it suppresses interference shared by both traces - such as ground bounce or EMI - without requiring matched driver circuits or differential amplifiers.
Can the LTC2364CDE-18#TRPBF operate with OVDD = 1.8V while VDD = 2.5V?
Yes - the LTC2364CDE-18#TRPBF fully supports independent OVDD (1.71V–5.25V) and VDD (2.375V–2.625V) supplies. At OVDD = 1.8V, digital inputs (CNV, SCK, CHAIN, RDL/SDI) recognize VIH ≥ 1.44V and VIL ≤ 0.36V, while SDO and BUSY outputs swing rail-to-rail, ensuring reliable interfacing with 1.8V FPGAs or microcontrollers.
What is the purpose of the exposed pad (Pin 17) on the LTC2364CDE-18#TRPBF DFN package?
The exposed pad (Pin 17) on the LTC2364CDE-18#TRPBF is electrically and thermally connected to GND. It must be soldered directly to a PCB ground plane to ensure proper thermal dissipation (θJA = 40°C/W) and low-impedance grounding for analog performance. Omitting this connection degrades SNR and risks thermal shutdown.
LTC2364CDE-18#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 18
- Sampling Rate (Per Second):
- 250k
- Number of Inputs:
- 1
- Input Type:
- Pseudo-Differential
- Data Interface:
- SPI
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External
- Voltage - Supply, Analog:
- 2.375V ~ 2.625V
- Voltage - Supply, Digital:
- 2.375V ~ 2.625V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 16-DFN (4x3)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2364CDE-18#TRPBF FAQ
1.How can I place an order for LTC2364CDE-18#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2364CDE-18#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2364CDE-18#TRPBF reliable?
The price and inventory of LTC2364CDE-18#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2364CDE-18#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2364CDE-18#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2364CDE-18#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2364CDE-18#TRPBF?
LTC2364CDE-18#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2364CDE-18#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2364CDE-18#TRPBF?
For technical support, including LTC2364CDE-18#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2364CDE-18#TRPBF requirements.
6.How does Aetrix verify that LTC2364CDE-18#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2364CDE-18#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2364CDE-18#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2364CDE-18#TRPBF?
All LTC2364CDE-18#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2364CDE-18#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2364CDE-18#TRPBF part is unused and in its original packaging.
Return procedure for LTC2364CDE-18#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2364CDE-18#TRPBF Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
