Analog Devices Inc. LTC2364CMS-18#PBF
- Part No.:
- LTC2364CMS-18#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 16-TFSOP (0.118", 3.00mm Width)
- Datasheet:
-
LTC2364CMS-18#PBF.pdf
- Description:
- IC ADC 18BIT SAR 16MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2364CMS-18#PBF from Analog Devices (formerly Linear Technology) is an 18-bit, 250ksps pseudo-differential unipolar successive approximation register (SAR) ADC operating from a single 2.5V supply. It delivers 97dB typical SNR, ±2.5LSB max INL, and guaranteed no missing codes at 18 bits, with VREF support from 2.5V to 5.1V. It is used in high-speed data acquisition systems requiring precision, low power, and wide dynamic range.
For engineers reviewing the LTC2364CMS-18#PBF datasheet, LTC2364CMS-18#PBF pinout, LTC2364CMS-18#PBF application, or LTC2364CMS-18#PBF equivalent, key selection considerations include its 250ksps throughput with zero cycle latency, SPI-compatible serial interface supporting 1.8V–5V I/O, internal conversion clock, and MSOP-16 package rated for 0°C to 70°C operation.
Technical Context
The LTC2364CMS-18#PBF implements a charge redistribution capacitor DAC (CDAC) architecture with pseudo-differential sampling, where IN+ accepts 0V to VREF input while IN– serves as ground sense (±100mV range). Conversion is initiated by a rising edge on CNV, and the internal oscillator eliminates external timing dependencies.
It features daisy-chain mode via CHAIN and RDL/SDI pins, supports straight-binary output, and auto-powers down between conversions-reducing current draw to 0.9µA in shutdown. Its 45pF analog input capacitance and 40Ω switch on-resistance define acquisition settling behavior, and it achieves 3.46µs transient response to full-scale step.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 18-bit - guarantees 262,144 distinct output levels with no missing codes across full temperature range. |
| Sampling Rate | 250ksps - enables real-time capture of signals up to 125kHz Nyquist bandwidth without pipeline delay. |
| SNR | 97dB (typ, fIN = 2kHz, VREF = 5V) - defines usable dynamic range of ~116dBFS for high-fidelity signal digitization. |
| INL | ±2.5LSB (max) - ensures monotonicity and linearity error ≤ ±48µV at 5V reference, critical for calibration-sensitive systems. |
| Power Dissipation | 3.4mW at 250ksps - enables battery-operated instrumentation with thermal budget under 5mW. |
| Reference Range | 2.5V to 5.1V - allows flexible scaling of input range (e.g., 0–5V or 0–2.5V) without external gain stages. |
| Supply Voltages | VDD = 2.5V (2.375–2.625V); OVDD = 1.71–5.25V - decouples analog core from digital I/O, enabling mixed-voltage system interfacing. |
Pinout & Package
Package: 16-lead plastic MSOP (4.0mm × 3.0mm), exposed pad not present (DFN variant has exposed GND pad; MSOP does not). Operating temperature range: 0°C to 70°C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CHAIN (1) | Mode selector | Low = normal mode (RDL/SDI = bus enable); high = daisy-chain mode (RDL/SDI = serial data input). |
| VDD (2) | Analog supply | 2.5V core supply; bypass with 10µF ceramic capacitor to GND for noise immunity. |
| GND (3,6,10,16) | Ground reference | Four dedicated GND pins minimize ground bounce and improve PSRR in high-speed sampling. |
| IN+ (4) | Pseudo-differential input (+) | Accepts 0V to VREF input; sees 45pF capacitance and 40Ω switch resistance during acquisition. |
| IN– (5) | Pseudo-differential input (–) | Ground-sense pin with ±100mV range; must connect to local ground plane or remote sense point. |
| REF (7,8) | Reference voltage input | Dual-pin connection for low-impedance 2.5–5.1V reference; requires 47µF X5R ceramic decoupling. |
| CNV (9) | Convert trigger | Rising-edge–initiated conversion; powers up ADC and starts acquisition phase. |
| BUSY (11) | Status indicator | Active-high open-drain output signaling conversion in progress; logic level referenced to OVDD. |
| RDL/SDI (12) | Configurable I/O | In normal mode: bus enable; in chain mode: serial data input for daisy-chained ADCs. |
| SCK (13) | Serial clock input | Accepts up to 100MHz SCK (10ns min period); controls timing of SDO data output MSB-first. |
| SDO (14) | Serial data output | Three-state output driven by OVDD; outputs 18-bit straight-binary code synchronized to SCK rising edges. |
| OVDD (15) | Digital I/O supply | 1.71–5.25V supply setting logic thresholds; bypass with 0.1µF capacitor to GND. |
Key Features
| Feature | Design Value |
|---|---|
| No cycle latency | Enables deterministic real-time control loops with immediate availability of conversion result after BUSY deassertion. |
| Auto power-down | Reduces supply current to 0.9µA between conversions, scaling power linearly with sample rate for burst-mode operation. |
| SPI-compatible interface | Supports 1.8V/2.5V/3.3V/5V logic without level shifters, simplifying integration into heterogeneous digital systems. |
| Internal conversion clock | Eliminates need for external timing circuitry or crystal oscillator, reducing BOM count and layout complexity. |
| Pseudo-differential input architecture | Rejects common-mode noise on IN+/IN– pair while maintaining unipolar 0V–VREF input range for simplified signal conditioning. |
Applications
| Medical Imaging Signal Chain | Industrial Process Monitoring |
|---|---|
Use Scenario: Digitizing low-noise analog outputs from CT/MRI sensor front-ends with minimal added distortion. IC Role / Device Role / Timing Role: High-resolution SAR ADC capturing 250ksps waveform data with 97dB SNR and <±2.5LSB INL for diagnostic accuracy. Use Value: Enables detection of sub-millivolt physiological signals without amplification-induced noise or harmonic artifacts. |
Use Scenario: Continuous monitoring of pressure, temperature, and flow transducers in PLC-based automation systems. IC Role / Device Role / Timing Role: Precision ADC interfacing with isolated analog inputs, delivering stable 18-bit codes over 0°C–70°C industrial ambient. Use Value: Eliminates calibration drift over time and temperature, supporting predictive maintenance with long-term measurement repeatability. |
| Portable Test Equipment | Battery-Powered Data Loggers |
Use Scenario: Handheld oscilloscopes and spectrum analyzers requiring high fidelity within tight power budgets. IC Role / Device Role / Timing Role: Low-power 18-bit ADC with 3.4mW active consumption and auto-shutdown, synchronized to portable UI refresh cycles. Use Value: Extends battery life beyond 8 hours per charge while preserving >93dB SINAD for field-deployable signal analysis. |
Use Scenario: Environmental sensors logging temperature, humidity, and gas concentration in remote locations. IC Role / Device Role / Timing Role: Ultra-low-quiescent ADC sampling at 250sps (3.4µW) during idle, waking only on event-triggered CNV pulses. Use Value: Achieves multi-year operation on coin-cell batteries by minimizing average current draw to <1µA in deep sleep. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 18-bit SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8860IDRCT | 16-bit resolution, 1MSPS, 1.8V supply only, no daisy-chain mode, 92dB SNR. | Higher speed but lower resolution; lacks CHAIN/RDL flexibility and extended VREF range. | Choose when throughput >250ksps is mandatory and 16-bit resolution suffices for cost-sensitive designs. |
| AD7960BCPZ-RL | 18-bit, 5MSPS, 5V supply, LVDS interface, 95.5dB SNR, requires external reference and clock. | Higher speed and SNR but demands complex layout, higher power (45mW), and no auto power-down. | Choose for high-channel-count, high-throughput systems where board space and power allow full differential LVDS routing. |
Compared with ADS8860IDRCT and AD7960BCPZ-RL, the LTC2364CMS-18#PBF uniquely balances 18-bit precision, 250ksps speed, ultra-low 3.4mW power, and integrated daisy-chain capability in a compact MSOP package-making it optimal for portable, battery-constrained, and multi-ADC channel applications where simplicity and thermal efficiency are critical.
Availability
LTC2364CMS-18#PBF is available at Aetrix Electronics and suitable for medical imaging signal chains, industrial process monitoring, and portable test equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LTC2364CMS-18#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2364-18 product line was designed for high-accuracy, low-power data acquisition in space-, power-, and thermal-constrained systems-emphasizing ease of use via internal clocking, flexible I/O voltage, and robust pseudo-differential input architecture.
FAQ
What is the maximum sampling rate of the LTC2364CMS-18#PBF?
The LTC2364CMS-18#PBF supports a maximum sampling rate of 250ksps with guaranteed performance across its full operating temperature range (0°C to 70°C). At this rate, conversion time is 1.9–3µs, and the minimum time between conversions (tCYC) is 4µs. No pipeline delay or cycle latency occurs, ensuring deterministic timing for real-time control applications.
Does the LTC2364CMS-18#PBF require an external clock source?
No, the LTC2364CMS-18#PBF includes an internal oscillator that sets the conversion timing, eliminating the need for an external clock source. This simplifies system design and reduces component count. The SCK pin remains required for serial data transfer but only governs the readout timing-not the conversion itself.
Can the LTC2364CMS-18#PBF operate with a 3.3V digital interface while using a 2.5V analog supply?
Yes. The LTC2364CMS-18#PBF separates analog (VDD = 2.5V) and digital I/O (OVDD = 1.71–5.25V) supplies. With OVDD = 3.3V, all digital pins (SCK, SDO, RDL/SDI, BUSY, CHAIN, CNV) comply with 3.3V logic levels while the analog core maintains optimal noise performance at 2.5V.
What is the input voltage range for the IN+ and IN– pins of the LTC2364CMS-18#PBF?
The IN+ pin accepts a pseudo-differential unipolar input from 0V to VREF (2.5V–5.1V). The IN– pin operates as a ground sense with an absolute range of ±100mV relative to GND and must be tied to the local ground plane or a remote ground reference point to maintain CMRR and avoid offset errors.
Is the LTC2364CMS-18#PBF pin-compatible with other variants in the LTC2364-18 family?
Yes-the LTC2364CMS-18#PBF shares identical pinout and footprint with all MSOP-packaged variants (e.g., LTC2364IMS-18#PBF, LTC2364HMS-18#PBF). Differences lie solely in temperature grade and internal trimming; no PCB redesign is needed when upgrading to wider-temperature versions.
LTC2364CMS-18#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-TFSOP (0.118", 3.00mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 18
- Sampling Rate (Per Second):
- 250k
- Number of Inputs:
- 1
- Input Type:
- Pseudo-Differential
- Data Interface:
- SPI
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External
- Voltage - Supply, Analog:
- 2.375V ~ 2.625V
- Voltage - Supply, Digital:
- 2.375V ~ 2.625V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 16-MSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2364CMS-18#PBF FAQ
1.How can I place an order for LTC2364CMS-18#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2364CMS-18#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2364CMS-18#PBF reliable?
The price and inventory of LTC2364CMS-18#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2364CMS-18#PBF is usually 5 days.
3.What payment methods are accepted for LTC2364CMS-18#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2364CMS-18#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2364CMS-18#PBF?
LTC2364CMS-18#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2364CMS-18#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2364CMS-18#PBF?
For technical support, including LTC2364CMS-18#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2364CMS-18#PBF requirements.
6.How does Aetrix verify that LTC2364CMS-18#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2364CMS-18#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2364CMS-18#PBF meets industry standards.
7.What is the process for return or replacement of LTC2364CMS-18#PBF?
All LTC2364CMS-18#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2364CMS-18#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2364CMS-18#PBF part is unused and in its original packaging.
Return procedure for LTC2364CMS-18#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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