Analog Devices Inc. LTC2367CDE-18#PBF
- Part No.:
- LTC2367CDE-18#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 16-WFDFN Exposed Pad
- Datasheet:
-
LTC2367CDE-18#PBF.pdf
- Description:
- IC ADC 18BIT SAR 16DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2367CDE-18#PBF from Analog Devices (formerly Linear Technology) is an 18-bit pseudo-differential unipolar successive approximation register (SAR) ADC with 500ksps throughput, 97dB typical SNR, ±2.5LSB max INL, and no missing codes. It operates from a single 2.5V supply, accepts 2.5V–5.1V external reference, and targets high-precision data acquisition in medical imaging and portable instrumentation.
For engineers reviewing the LTC2367CDE-18#PBF datasheet, LTC2367CDE-18#PBF pinout, LTC2367CDE-18#PBF application, or LTC2367CDE-18#PBF equivalent, key selection criteria include guaranteed 18-bit no-missing-codes operation, low 6.8mW power at full speed, SPI-compatible daisy-chain interface, internal conversion clock, and 0°C to 70°C temperature grade in 4mm × 3mm DFN package.
Technical Context
The LTC2367CDE-18#PBF implements a charge-redistribution SAR architecture with pseudo-differential sampling: IN+ accepts 0V to VREF, while IN– serves as ground-sense input with ±100mV range. Conversion is initiated by CNV rising edge and completed in 1.5µs with zero cycle latency.
It features dual-supply operation-2.5V VDD for analog core and 1.71V–5.25V OVDD for digital I/O-enabling interoperability with 1.8V/2.5V/3.3V/5V logic. An internal oscillator eliminates external clock dependency, and automatic power-down between conversions scales quiescent current to sampling rate.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 18-bit-guarantees monotonic transfer function and no missing codes across full temperature range. |
| Sampling Rate | 500ksps-supports real-time acquisition of signals up to 250kHz Nyquist bandwidth without undersampling. |
| SNR | 97dB typical at fIN = 2kHz, VREF = 5V-enables >15.8 effective number of bits (ENOB) for high-fidelity signal capture. |
| INL | ±2.5LSB maximum-ensures accurate amplitude representation in precision measurement applications. |
| Power Dissipation | 6.8mW at 500ksps-achieves <14µW per sample, critical for battery-powered instrumentation. |
| Reference Range | 2.5V to 5.1V-allows flexible full-scale scaling while maintaining 19µV LSB size at 5V reference. |
| Operating Temp | 0°C to 70°C-validated performance for commercial-grade embedded systems and test equipment. |
Pinout & Package
Package: 16-lead (4mm × 3mm) plastic DFN with exposed pad (Pin 17), RoHS-compliant, JEDEC MO-220 variant DE. Exposed pad must be soldered to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CHAIN (1) | Mode selector | High enables daisy-chain mode (RDL/SDI becomes serial input); low enables normal bus-enable mode. |
| VDD (2) | Analog supply | 2.375V–2.625V, powers SAR core and reference buffer; requires 10µF ceramic bypass to GND. |
| GND (3,6,10,16) | Ground return | Four dedicated analog/digital ground pins minimize noise coupling and ensure stable reference path. |
| IN+ (4) | Differential analog input | Accepts 0V to VREF input voltage; sampled via 45pF capacitor and 40Ω switch during acquisition phase. |
| IN– (5) | Ground sense | ±100mV range relative to GND; must connect to system ground or remote ground sense point. |
| REF (7,8) | Reference input | 2.5V–5.1V external reference; draws up to 0.32mA at 500ksps; requires 47µF X5R ceramic decoupling. |
| CNV (9) | Convert trigger | Rising-edge–initiated conversion; minimum pulse width 20ns; powers up ADC and starts acquisition. |
| BUSY (11) | Status indicator | Active-high open-drain output signaling conversion in progress; logic level referenced to OVDD. |
| RDL/SDI (12) | Configurable I/O | In normal mode: bus enable control; in chain mode: serial data input for daisy-chained ADCs. |
| SCK (13) | Serial clock | Supports up to 100MHz SCK frequency; timing defined by OVDD; controls MSB-first data shift-out on SDO. |
| SDO (14) | Serial data output | 18-bit straight-binary result shifted out MSB first; valid 9.5ns after SCK↑; driven to OVDD/GND levels. |
| OVDD (15) | Digital I/O supply | 1.71V–5.25V interface supply; sets logic thresholds for all digital pins; bypass with 0.1µF capacitor. |
| GND (17) | Exposed pad | Thermal and electrical ground connection; mandatory soldering to PCB ground plane for thermal dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| No pipeline delay | Zero-cycle latency ensures deterministic timing for real-time control loops and triggered acquisition. |
| SPI-compatible interface | Native support for 1.8V/2.5V/3.3V/5V logic levels eliminates level-shifter requirements in mixed-voltage systems. |
| Daisy-chain mode | Enables synchronous multi-channel sampling with single SCK and CNV lines-reduces MCU GPIO count and routing complexity. |
| Internal conversion clock | Removes need for external timing circuitry, simplifying layout and improving jitter immunity in noise-sensitive environments. |
| Auto power-down | Reduces current to 0.9µA between conversions-critical for burst-mode sensing in energy-constrained IoT endpoints. |
| Pseudo-differential input | Rejects common-mode noise on IN+/IN– pair while enabling single-ended signal conditioning with low-distortion buffers like LT6202. |
Applications
| Medical Imaging Signal Chain | Portable High-Speed Data Logger |
|---|---|
Use Scenario: Digitizing low-noise analog outputs from ultrasound transducer front-ends or MRI gradient amplifiers requiring high dynamic range and minimal harmonic distortion. IC Role / Device Role / Timing Role: Primary 18-bit digitizer capturing baseband signals up to 250kHz with 97dB SNR and –120dB THD. Use Value: Enables detection of weak tissue echoes or subtle magnetic field variations without signal degradation from quantization or harmonic artifacts. |
Use Scenario: Battery-powered field instrument recording vibration, acoustic emission, or environmental sensor data over extended periods. IC Role / Device Role / Timing Role: Low-power SAR ADC performing 500ksps bursts followed by deep sleep, synchronized via CNV edge. Use Value: Achieves 15.8 ENOB at 6.8mW full-speed operation, extending battery life while preserving fidelity for post-processing analysis. |
| Industrial Process Monitoring | Automated Test Equipment (ATE) |
Use Scenario: High-accuracy monitoring of pressure, temperature, or flow transducers in factory automation systems where long-term stability and linearity are critical. IC Role / Device Role / Timing Role: Precision unipolar ADC interfacing with low-drift references (e.g., LTC6655-5) and op-amp drivers for sensor signal conditioning. Use Value: ±2.5LSB INL and 0.02LSB/°C zero-scale drift ensure calibration validity over wide ambient temperature swings (0°C–70°C). |
Use Scenario: Channel expansion in modular ATE platforms requiring synchronized multi-channel sampling with minimal board space. IC Role / Device Role / Timing Role: Daisy-chained ADC node providing time-aligned 18-bit samples across multiple channels using shared SCK/CNV. Use Value: Eliminates inter-channel skew and reduces FPGA resource usage by offloading timing alignment to hardware daisy-chain protocol. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 18-bit SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8860IDRCT | 16-bit resolution, 1MSPS, 2.5V supply, SPI interface; lower power (2.5mW) but 2-bit lower resolution and no daisy-chain mode. | Best suited for cost-sensitive, lower-resolution applications where 16-bit ENOB suffices and multi-ADC synchronization is handled externally. | Select when system SNR requirement is ≤90dB and board space constraints favor smaller 3mm × 3mm QFN package. |
| AD7606C-18BSTZ | 8-channel simultaneous-sampling 18-bit SAR, 1MSPS per channel, parallel/SPI interface; higher integration but 120mW power and larger 64-lead LQFP. | Targets multi-sensor systems needing true simultaneous capture (e.g., motor phase currents), not single-channel high-speed acquisition. | Choose when channel count >1 and strict inter-channel phase matching is required-LTC2367CDE-18#PBF remains optimal for single-channel 500ksps with minimal footprint. |
Compared with ADS8860IDRCT and AD7606C-18BSTZ, the LTC2367CDE-18#PBF uniquely balances 18-bit no-missing-codes assurance, ultra-low 6.8mW active power, compact DFN packaging, and hardware daisy-chain support-making it the preferred choice for space-constrained, battery-aware, single-channel high-fidelity acquisition.
Availability
LTC2367CDE-18#PBF is available at Aetrix Electronics and suitable for medical imaging signal chains, portable high-speed data loggers, and industrial process monitoring requiring stable component supply, RoHS compliance, and commercial-temperature-grade reliability.
Supply support for LTC2367CDE-18#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2367-18 product line delivers ultra-low-noise, low-power 18-bit SAR ADCs optimized for precision data acquisition in space- and energy-constrained systems-emphasizing guaranteed no-missing-codes operation, internal timing, and flexible I/O voltage compatibility.
FAQ
What is the operating temperature range for the LTC2367CDE-18#PBF?
The LTC2367CDE-18#PBF is specified for 0°C to 70°C operation-the "C" grade designation confirms commercial-temperature qualification. All DC and AC specifications, including ±2.5LSB INL and 97dB SNR, are guaranteed across this full range per the datasheet's "l" notation.
Does the LTC2367CDE-18#PBF require an external clock source?
No, the LTC2367CDE-18#PBF integrates an internal oscillator that sets conversion timing-eliminating external clock dependencies. The SCK pin only controls serial data transfer timing; conversion start and duration are fully self-timed, easing system-level timing design.
Can the LTC2367CDE-18#PBF interface directly with a 1.8V microcontroller?
Yes. The LTC2367CDE-18#PBF supports 1.71V–5.25V OVDD, allowing direct connection to 1.8V logic. VIH and VIL thresholds scale with OVDD (0.8×OVDD and 0.2×OVDD), and SDO output drives to OVDD/GND levels-no level-shifting circuitry is needed.
What reference voltage options are supported by the LTC2367CDE-18#PBF?
The LTC2367CDE-18#PBF accepts 2.5V to 5.1V external reference voltage on the REF pins. At 5V reference, LSB size is 19µV; at 2.5V, LSB is 9.5µV. Reference current draw is 0.24–0.32mA at 500ksps, requiring robust decoupling (47µF X5R ceramic) per datasheet guidelines.
How does the daisy-chain mode work on the LTC2367CDE-18#PBF?
When CHAIN (Pin 1) is high, RDL/SDI becomes SDI and SDO drives daisy-chain data. Multiple LTC2367CDE-18#PBF devices share one SCK and CNV line; BUSY signals cascade to synchronize readout. Each device shifts its 18-bit result into the next, enabling synchronized multi-channel capture with minimal interface lines.
LTC2367CDE-18#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 18
- Sampling Rate (Per Second):
- 500k
- Number of Inputs:
- 1
- Input Type:
- Pseudo-Differential
- Data Interface:
- SPI
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External
- Voltage - Supply, Analog:
- 2.375V ~ 2.625V
- Voltage - Supply, Digital:
- 2.375V ~ 2.625V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 16-DFN (4x3)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2367CDE-18#PBF FAQ
1.How can I place an order for LTC2367CDE-18#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2367CDE-18#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2367CDE-18#PBF reliable?
The price and inventory of LTC2367CDE-18#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2367CDE-18#PBF is usually 5 days.
3.What payment methods are accepted for LTC2367CDE-18#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2367CDE-18#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2367CDE-18#PBF?
LTC2367CDE-18#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2367CDE-18#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2367CDE-18#PBF?
For technical support, including LTC2367CDE-18#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2367CDE-18#PBF requirements.
6.How does Aetrix verify that LTC2367CDE-18#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2367CDE-18#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2367CDE-18#PBF meets industry standards.
7.What is the process for return or replacement of LTC2367CDE-18#PBF?
All LTC2367CDE-18#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2367CDE-18#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2367CDE-18#PBF part is unused and in its original packaging.
Return procedure for LTC2367CDE-18#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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