Analog Devices Inc. LTC2367CMS-18#PBF
- Part No.:
- LTC2367CMS-18#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 16-TFSOP (0.118", 3.00mm Width)
- Datasheet:
-
LTC2367CMS-18#PBF.pdf
- Description:
- IC ADC 18BIT SAR 16MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2367CMS-18#PBF from Analog Devices (formerly Linear Technology) is an 18-bit pseudo-differential unipolar successive approximation register (SAR) ADC with 500ksps throughput, 97dB SNR (typ), ±2.5LSB INL (max), and operation from a single 2.5V supply. It supports VREF from 2.5V to 5.1V and delivers no missing codes at full 18-bit resolution-ideal for high-speed medical imaging and portable instrumentation requiring precision DC-to-mid-frequency acquisition.
For engineers reviewing the LTC2367CMS-18#PBF datasheet, LTC2367CMS-18#PBF pinout, LTC2367CMS-18#PBF application, or LTC2367CMS-18#PBF equivalent, key selection criteria include guaranteed 18-bit monotonicity, daisy-chain SPI interface compatibility with 1.8V–5V logic, internal conversion clock eliminating external timing constraints, and low 6.8mW power dissipation at full speed.
Technical Context
The LTC2367CMS-18#PBF implements a charge-redistribution SAR architecture with a pseudo-differential input stage where IN+ accepts 0V to VREF while IN– operates as a ground-sense node (±100mV range). Conversion is initiated by a rising edge on CNV, with no pipeline delay and fixed 1.5µs conversion time set by an internal oscillator.
Its SPI-compatible serial interface supports both normal mode (RDL/SDI as bus enable) and daisy-chain mode (RDL/SDI as SDI), with SDO outputting straight-binary 18-bit data MSB-first on SCK rising edges. Power management includes automatic power-down between conversions, scaling idle current to ≤140µA in shutdown.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 18-bit - guarantees monotonic transfer function and no missing codes across full temperature range. |
| Sampling Rate | 500ksps - enables real-time capture of signals up to 250kHz Nyquist bandwidth without undersampling. |
| SNR | 97dB (typ, fIN = 2kHz, VREF = 5V) - defines effective noise floor of ~1.3LSBRMS for high-fidelity signal digitization. |
| INL | ±2.5LSB (max) - limits integral nonlinearity error to <0.01% of full-scale, critical for calibration-sensitive systems. |
| Power Dissipation | 6.8mW at 500ksps - enables battery-operated designs with thermal budget under 10mW at full throughput. |
| VREF Range | 2.5V to 5.1V - allows flexible system-level scaling: 5V reference yields 19µV/LSB; 2.5V yields 9.5µV/LSB. |
| Supply Voltages | VDD = 2.5V (2.375–2.625V); OVDD = 1.71–5.25V - decouples analog core from digital I/O, enabling mixed-voltage host interfacing. |
Pinout & Package
Package: 16-lead MSOP (small-outline package), 3mm × 4.9mm body, exposed pad not present (DFN variant has exposed GND pad; MSOP does not).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CHAIN (1) | Mode selector | High = daisy-chain mode (RDL/SDI becomes serial data input); Low = normal mode (RDL/SDI enables SDO tri-state). |
| VDD (2) | Analog core supply | 2.5V ±62.5mV supply for SAR core and reference buffer; requires 10µF ceramic bypass to GND. |
| GND (3,6,10,16) | Analog/digital ground | Four dedicated GND pins minimize ground bounce; must be connected to low-impedance ground plane. |
| IN+ (4) | Pseudo-differential input (+) | Accepts 0V to VREF; sampling capacitance 45pF with 40Ω switch resistance during acquisition. |
| IN– (5) | Pseudo-differential input (–) | Ground-sense node with ±100mV range; ties to remote ground or local GND to reject common-mode noise. |
| REF (7,8) | Reference voltage inputs | Dual-pin connection for low-inductance 2.5–5.1V reference; requires 47µF X5R ceramic capacitor at pin. |
| CNV (9) | Convert trigger | Rising-edge–sensitive; initiates acquisition and conversion; minimum pulse width 20ns. |
| BUSY (11) | Conversion status indicator | Active-high open-drain output; asserts at CNV↑, deasserts after 1.5µs conversion completes. |
| RDL/SDI (12) | Serial interface control/data | In normal mode: bus enable; in chain mode: serial data input from upstream ADC in daisy chain. |
| SCK (13) | Serial clock input | Accepts 10ns min period (100MHz max); controls SDO timing; logic levels referenced to OVDD. |
| SDO (14) | Serial data output | 18-bit straight-binary output MSB-first; tri-stated when RDL/SDI = low in normal mode. |
| OVDD (15) | I/O interface supply | 1.71–5.25V digital supply; sets VIH/VIL thresholds and drives SDO/BUSY outputs. |
Key Features
| Feature | Design Value |
|---|---|
| No missing codes at 18 bits | Guaranteed monotonicity over full temperature range (0°C to 70°C for CMS grade), eliminating code ambiguities in closed-loop control. |
| Internal conversion clock | Eliminates need for external timing circuitry or master clock synchronization-reduces BOM count and layout complexity. |
| Daisy-chain SPI mode | Enables multi-ADC synchronization with single SCK/SCKCH line and cascaded SDO→SDI routing-ideal for channel expansion in DAQ systems. |
| Auto power-down between conversions | Reduces average power proportionally to sampling rate: 6.8µW at 500sps enables ultra-low-power wake-on-event sensing. |
| Pseudo-differential input architecture | Rejects common-mode noise on IN+/IN– pair while maintaining unipolar 0V–VREF dynamic range-simplifies front-end design vs true differential ADCs. |
Applications
| Medical Imaging Signal Acquisition | Portable High-Precision Instrumentation |
|---|---|
Use Scenario: Digitizing low-noise analog outputs from ultrasound transducer receive chains or MRI gradient monitoring sensors. IC Role / Device Role / Timing Role: Primary high-resolution ADC capturing baseband signals up to 250kHz with minimal added noise or distortion. Use Value: 97dB SNR and –120dB THD preserve weak signal integrity; 18-bit resolution enables >100dB dynamic range for tissue contrast differentiation. | Use Scenario: Battery-powered handheld multimeters, portable spectrum analyzers, or field-deployable sensor loggers. IC Role / Device Role / Timing Role: Core data converter interfacing with low-power microcontrollers via SPI, operating in burst-sampling mode. Use Value: 6.8mW active power and 140µA shutdown current extend battery life; daisy-chain support simplifies multi-channel expansion without extra GPIOs. |
| Industrial Process Control Monitoring | Automated Test Equipment (ATE) |
Use Scenario: Real-time monitoring of pressure, temperature, and flow transducers in PLC analog input modules. IC Role / Device Role / Timing Role: High-accuracy ADC embedded in isolated analog front-ends, synchronized to system controller via CNV edge. Use Value: ±2.5LSB INL ensures traceable calibration across temperature; guaranteed operation to 70°C meets industrial ambient requirements. | Use Scenario: Channelized digitizer cards in benchtop ATE systems requiring simultaneous sampling across multiple DUTs. IC Role / Device Role / Timing Role: One of multiple synchronized LTC2367CMS-18#PBF devices in daisy-chain configuration sharing SCK and CNV. Use Value: No cycle latency and deterministic 1.5µs conversion time enable precise inter-channel timing alignment within <1ns jitter. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 18-bit SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8860IDRCT | 16-bit resolution, 1MSPS, SPI interface, 2.5V supply, 92dB SNR (typ), no daisy-chain mode. | Higher speed but lower resolution; lacks chain mode and 18-bit monotonicity guarantee. | Select when 16-bit resolution suffices and >500ksps is required; avoid if 18-bit no-missing-codes compliance is mandatory. |
| AD7606C-18BSTZ | 8-channel simultaneous-sampling, 18-bit, 1MSPS per channel, parallel + SPI interface, ±10V bipolar input, 2.5V/5V supplies. | Multi-channel, bipolar input, higher power (120mW), larger 64-lead LQFP package. | Select for multi-channel synchronized acquisition; avoid for space-constrained single-channel designs needing MSOP footprint. |
Compared with ADS8860IDRCT and AD7606C-18BSTZ, the LTC2367CMS-18#PBF uniquely balances 18-bit guaranteed monotonicity, ultra-low 6.8mW power, compact MSOP packaging, and hardware daisy-chain capability-making it optimal for single-channel, battery-aware, high-fidelity acquisition where board area and deterministic timing are critical.
Availability
LTC2367CMS-18#PBF is available at Aetrix Electronics and suitable for medical imaging signal acquisition, portable high-precision instrumentation, and industrial process control monitoring requiring stable component supply and long-term production continuity.
Supply support for LTC2367CMS-18#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC2367-18 product line was designed for high-speed, low-power, high-accuracy data acquisition in space- and energy-constrained systems-emphasizing guaranteed 18-bit performance, simplified timing, and robust operation across extended temperature ranges.
FAQ
What is the maximum sampling rate supported by the LTC2367CMS-18#PBF?
The LTC2367CMS-18#PBF supports a maximum sampling rate of 500ksps, with a fixed 1.5µs conversion time and no pipeline delay. This enables full 18-bit resolution sampling at precisely 2µs intervals (tCYC = 2µs), making it suitable for real-time acquisition of signals up to 250kHz without aliasing.
Does the LTC2367CMS-18#PBF require an external clock source for conversion timing?
No, the LTC2367CMS-18#PBF integrates an internal oscillator that sets the conversion time deterministically at 1.5µs. External clocking is unnecessary for core ADC operation-only the SPI serial clock (SCK) must be supplied by the host for data readout, simplifying system timing architecture.
What is the purpose of the CHAIN pin on the LTC2367CMS-18#PBF?
The CHAIN pin (Pin 1) configures the LTC2367CMS-18#PBF's serial interface mode: when pulled high, it enables daisy-chain mode where RDL/SDI functions as SDI input for cascading multiple ADCs; when low, it enables normal mode where RDL/SDI acts as a bus-enable control for SDO tri-state. Logic levels are referenced to OVDD.
Can the LTC2367CMS-18#PBF operate with a 3.3V digital interface while using a 2.5V analog supply?
Yes-the LTC2367CMS-18#PBF separates analog (VDD = 2.5V) and digital I/O (OVDD = 1.71–5.25V) supplies. With OVDD = 3.3V, VIH/VIL thresholds scale accordingly (VIH ≥ 2.64V, VIL ≤ 0.66V), allowing seamless interfacing to 3.3V microcontrollers without level shifters.
Is the LTC2367CMS-18#PBF pin-compatible with other variants in the LTC2367-18 family?
Yes-the LTC2367CMS-18#PBF shares identical 16-lead MSOP pinout and functionality with LTC2367IMS-18#PBF (–40°C to 85°C) and LTC2367HMS-18#PBF (–40°C to 125°C). Only temperature grade and screening differ; no PCB redesign is needed when upgrading to wider temperature ranges.
LTC2367CMS-18#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-TFSOP (0.118", 3.00mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 18
- Sampling Rate (Per Second):
- 500k
- Number of Inputs:
- 1
- Input Type:
- Pseudo-Differential
- Data Interface:
- SPI
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External
- Voltage - Supply, Analog:
- 2.375V ~ 2.625V
- Voltage - Supply, Digital:
- 2.375V ~ 2.625V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 16-MSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2367CMS-18#PBF FAQ
1.How can I place an order for LTC2367CMS-18#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2367CMS-18#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2367CMS-18#PBF reliable?
The price and inventory of LTC2367CMS-18#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2367CMS-18#PBF is usually 5 days.
3.What payment methods are accepted for LTC2367CMS-18#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2367CMS-18#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2367CMS-18#PBF?
LTC2367CMS-18#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2367CMS-18#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2367CMS-18#PBF?
For technical support, including LTC2367CMS-18#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2367CMS-18#PBF requirements.
6.How does Aetrix verify that LTC2367CMS-18#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2367CMS-18#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2367CMS-18#PBF meets industry standards.
7.What is the process for return or replacement of LTC2367CMS-18#PBF?
All LTC2367CMS-18#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2367CMS-18#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2367CMS-18#PBF part is unused and in its original packaging.
Return procedure for LTC2367CMS-18#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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