Analog Devices Inc. LTC2380CDE-16#PBF
- Part No.:
- LTC2380CDE-16#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 16-WFDFN Exposed Pad
- Datasheet:
-
LTC2380CDE-16#PBF.pdf
- Description:
- IC ADC 16BIT SAR 16DFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,776
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2380CDE-16#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, 2 Msps successive approximation register (SAR) analog-to-digital converter with fully differential ±VREF input, 96.2 dB SNR, ±0.6 LSB INL max, and digital gain compression (DGC) for single-supply amplifier interfacing. It operates from a 2.5 V analog supply and supports 1.8 V–5 V I/O logic, targeting high-speed data acquisition in compact instrumentation and medical imaging systems.
For engineers reviewing the LTC2380CDE-16#PBF datasheet, LTC2380CDE-16#PBF pinout, LTC2380CDE-16#PBF application, or LTC2380CDE-16#PBF equivalent, key selection criteria include guaranteed 16-bit no-missing-codes operation, daisy-chain SPI interface compatibility, internal conversion clock, DGC-enabled 0.5 V–4.5 V input range (at VREF = 5 V), and 4 mm × 3 mm DFN package with exposed thermal pad.
Technical Context
The LTC2380CDE-16#PBF implements a charge redistribution SAR architecture with a 16-bit CDAC and differential comparator, achieving zero-cycle latency and no pipeline delay. Its internal oscillator eliminates external clock dependency, while auto power-down between conversions scales quiescent current from 7.5 mA at 2 Msps to 0.9 µA in sleep mode.
Digital Gain Compression (DGC) is controlled via the REF/DGC pin: grounded enables 10%–90% full-scale mapping (e.g., 0.5 V–4.5 V for 5 V reference), preserving 16-bit resolution without requiring negative supply for driving amplifiers. The device supports both normal and daisy-chain SPI modes via the CHAIN pin, with SDO output in 2's complement format.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit - delivers 65,536 discrete output levels with guaranteed no missing codes across temperature. |
| Sampling Rate | 2 Msps - enables real-time digitization of signals up to 1 MHz Nyquist bandwidth with minimal latency. |
| SNR | 96.2 dB (typ, fIN = 2 kHz, VREF = 5 V) - supports >15.7 ENOB for precision measurement applications. |
| INL | ±0.6 LSB (max) - ensures monotonicity and accurate end-point linearity critical for closed-loop control. |
| Power Dissipation | 19 mW at 2 Msps - low active power enables battery-operated or thermally constrained designs. |
| Input Range | ±VREF, VREF = 2.5 V to 5.1 V - flexible reference scaling accommodates diverse signal conditioning topologies. |
| DGC Function | Enabled by grounding REF/DGC - maps full-scale to 0.1×VREF to 0.9×VREF, enabling single-supply amplifier drive (e.g., 5.5 V). |
Pinout & Package
Package: 16-lead (4 mm × 3 mm) plastic DFN with exposed thermal pad (Pin 17), rated for 0°C to 70°C operation. Exposed pad must be soldered to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CHAIN) | Chain Mode Selector | High enables daisy-chain SPI mode; low configures RDL/SDI as bus enable, supporting multi-ADC synchronization. |
| 2 (VDD) | Analog Supply | 2.375 V–2.625 V supply powering core ADC circuitry; requires 10 µF ceramic bypass to GND. |
| 4,5 (IN+, IN–) | Differential Analog Inputs | Accept ±VREF fully differential signal; input capacitance 45 pF (sample), 5 pF (hold); common-mode range = VREF/2 ± 0.1 V. |
| 7 (REF) | Reference Input | 2.5 V–5.1 V external reference; decoupled with 47 µF X5R ceramic capacitor; sets full-scale range and LSB size (152 µV at 5 V). |
| 8 (REF/DGC) | Reference/DGC Control | Tied to GND enables digital gain compression (0.5 V–4.5 V input range at 5 V ref); tied to REF disables DGC for standard ±5 V range. |
| 9 (CNV) | Convert Trigger | Rising-edge initiated conversion; powers up ADC and starts sampling; timing-critical for deterministic throughput. |
| 11 (BUSY) | Conversion Status | Active-high open-drain indicator; asserts at CNV↑, deasserts when 16-bit result is ready on SDO. |
| 12 (RDL/SDI) | Serial Data Control/Input | In normal mode: bus enable for SDO tri-state; in chain mode: serial data input from upstream ADC. |
| 13 (SCK) | Serial Clock | 100 MHz max SPI-compatible clock; rising-edge sampled; supports 1.8 V–5 V logic levels via OVDD. |
| 14 (SDO) | Serial Data Output | 2's complement 16-bit result shifted MSB-first on SCK↑; tri-stated when RDL/SDI = low in normal mode. |
| 15 (OVDD) | I/O Supply | 1.71 V–5.25 V digital interface supply; sets logic thresholds for all digital pins; bypassed with 0.1 µF capacitor. |
| 3,6,10,16 (GND) | Analog/Digital Ground | Four dedicated ground pins minimize noise coupling; exposed pad (Pin 17) is GND and mandatory for thermal management. |
Key Features
| Feature | Design Value |
|---|---|
| No cycle latency | Immediate data availability after conversion completes-no pipelining delay simplifies timing-critical control loops. |
| Digital Gain Compression (DGC) | Eliminates need for dual-rail amplifier supplies by digitally remapping full-scale to 10%–90% of VREF, reducing system BOM and layout complexity. |
| Internal conversion clock | Removes requirement for external timing source-reduces component count and jitter sensitivity in high-SNR applications. |
| Auto power-down | Reduces current from 7.5 mA (2 Msps) to 0.9 µA (sleep), enabling adaptive power management in burst-mode acquisition. |
| SPI daisy-chain mode | Enables synchronized sampling across multiple LTC2380CDE-16#PBF devices using single SCK/SCKCH and cascaded SDO→SDI routing. |
| Guaranteed operation to 125°C (H-grade variants) | While LTC2380CDE-16#PBF is rated 0°C–70°C, same-pinout H-grade versions support extended industrial environments. |
Applications
| Medical Imaging Signal Chain | Portable High-Speed DAQ |
|---|---|
|
Use Scenario: Digitizing ultrasound echo return signals or MRI gradient coil feedback in handheld or cart-based systems. IC Role / Device Role / Timing Role: Primary 16-bit SAR ADC capturing transient analog waveforms at ≥1 Msps with <100 ps aperture jitter. Use Value: 96.2 dB SNR and –117 dB THD preserve weak signal integrity; DGC allows single-supply front-end amplifiers, shrinking PCB area and cost. |
Use Scenario: Battery-powered oscilloscope modules or field-deployable sensor nodes acquiring vibration, acoustic, or ECG waveforms. IC Role / Device Role / Timing Role: Low-power, high-throughput ADC interfaced to ARM Cortex-M microcontrollers via SPI. Use Value: 19 mW active power and 0.9 µA sleep current extend runtime; 2 Msps rate captures transients without undersampling artifacts. |
| Industrial Process Monitoring | Automated Test Equipment (ATE) |
|
Use Scenario: Real-time monitoring of motor phase currents, pressure transducer outputs, or thermal sensor arrays in PLC edge nodes. IC Role / Device Role / Timing Role: Precision ADC in isolated analog front-end, referenced to stable 5 V LDO, with ±0.6 LSB INL ensuring calibration stability. Use Value: Fully differential inputs reject common-mode noise from long cables; 83 dB CMRR suppresses 50/60 Hz interference in factory environments. |
Use Scenario: High-channel-count ATE systems requiring synchronized, multi-device sampling for parametric testing of ICs or RF components. IC Role / Device Role / Timing Role: One of multiple LTC2380CDE-16#PBF units in daisy-chain configuration, sharing SCK and driven by single CNV pulse. Use Value: Daisy-chain mode reduces FPGA GPIO count and routing congestion; identical 278 ns conversion time ensures inter-device skew <1 ns. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7960BCPZ-RL7 | 18-bit, 5 Msps, 2.5 V supply, no DGC, LVDS interface (not SPI), higher power (43 mW), larger 40-lead LFCSP package. | Higher resolution and speed suit metrology-grade test equipment; LVDS interface requires differential routing and termination. | Select AD7960BCPZ-RL7 only when >16-bit ENOB and >2 Msps are required; avoid if SPI compatibility, DGC, or DFN footprint are design constraints. |
| ADS8860IRGET | 16-bit, 1 Msps, 2.5–5 V supply, SPI interface, no DGC, 10 mW power, 20-lead VQFN (3.5 × 3.5 mm), lower SNR (92.5 dB). | Lower throughput and SNR fit cost-sensitive portable instruments where 1 Msps suffices and DGC is unnecessary. | Choose ADS8860IRGET for simpler, lower-cost designs with relaxed speed/noise requirements; not suitable for 2 Msps or DGC-dependent amplifier topologies. |
Compared with AD7960BCPZ-RL7, LTC2380CDE-16#PBF offers SPI compatibility, DGC, and smaller DFN packaging at lower power-but trades off 2 bits of resolution and 3 Msps speed. Against ADS8860IRGET, it delivers +1 Msps, +3.7 dB SNR, and DGC functionality at modest cost premium.
Availability
LTC2380CDE-16#PBF is available at Aetrix Electronics and suitable for medical imaging signal chains, portable high-speed data acquisition, and industrial process monitoring requiring stable component supply, consistent DFN packaging, and guaranteed 0°C to 70°C operation.
Supply support for LTC2380CDE-16#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, formed through the acquisition of Linear Technology in 2017.
The LTC2380-16 family was designed to address high-speed, low-power, precision data acquisition in space-constrained, thermally sensitive applications-emphasizing ease of use via integrated features like DGC, internal clock, and flexible SPI interface.
FAQ
What is the operating temperature range for the LTC2380CDE-16#PBF?
The LTC2380CDE-16#PBF is specified for 0°C to 70°C ambient operation. This commercial-grade temperature range is defined by the "C" suffix in the part number and applies to the 4 mm × 3 mm DFN package variant. For extended ranges, consider LTC2380IDE-16#PBF (–40°C to 85°C) or LTC2380HMS-16#PBF (–40°C to 125°C), though those use MSOP packaging.
Does the LTC2380CDE-16#PBF require an external clock for conversion timing?
No, the LTC2380CDE-16#PBF does not require an external clock for conversion timing. It integrates an internal oscillator that sets the 278 ns conversion time (tCONV). External timing is only needed for the SPI interface (SCK) and CNV trigger-simplifying system design and reducing jitter-sensitive clock distribution.
How does Digital Gain Compression (DGC) work in the LTC2380CDE-16#PBF?
Digital Gain Compression (DGC) in the LTC2380CDE-16#PBF is enabled by grounding the REF/DGC pin (Pin 8). This remaps the full-scale input range from ±VREF to 0.1×VREF–0.9×VREF (e.g., 0.5 V–4.5 V at VREF = 5 V), allowing single-supply amplifiers (e.g., LT6350 on +5.5 V) to drive the ADC without negative rails-preserving all 16 bits of resolution.
What is the significance of the exposed pad (Pin 17) on the LTC2380CDE-16#PBF DFN package?
The exposed pad (Pin 17) on the LTC2380CDE-16#PBF is electrically and thermally connected to GND. It must be soldered directly to the PCB ground plane to ensure proper thermal dissipation (θJA = 40°C/W) and low-impedance grounding for analog performance. Omitting this connection risks thermal overload and increased noise or INL error.
Can the LTC2380CDE-16#PBF interface with 1.8 V logic microcontrollers?
Yes, the LTC2380CDE-16#PBF supports 1.8 V logic-level interfaces via its OVDD pin (Pin 15), which accepts 1.71 V–5.25 V. When OVDD = 1.8 V, all digital inputs (CNV, SCK, CHAIN, RDL/SDI) recognize 0.8×OVDD = 1.44 V as VIH min and 0.2×OVDD = 0.36 V as VIL max, ensuring reliable communication with 1.8 V MCUs without level shifters.
LTC2380CDE-16#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 16
- Sampling Rate (Per Second):
- 2M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- SPI
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External
- Voltage - Supply, Analog:
- 1.71V ~ 5.25V
- Voltage - Supply, Digital:
- 1.71V ~ 5.25V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 16-DFN (4x3)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2380CDE-16#PBF FAQ
1.How can I place an order for LTC2380CDE-16#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2380CDE-16#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2380CDE-16#PBF reliable?
The price and inventory of LTC2380CDE-16#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2380CDE-16#PBF is usually 5 days.
3.What payment methods are accepted for LTC2380CDE-16#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2380CDE-16#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2380CDE-16#PBF?
LTC2380CDE-16#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2380CDE-16#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2380CDE-16#PBF?
For technical support, including LTC2380CDE-16#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2380CDE-16#PBF requirements.
6.How does Aetrix verify that LTC2380CDE-16#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2380CDE-16#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2380CDE-16#PBF meets industry standards.
7.What is the process for return or replacement of LTC2380CDE-16#PBF?
All LTC2380CDE-16#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2380CDE-16#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2380CDE-16#PBF part is unused and in its original packaging.
Return procedure for LTC2380CDE-16#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2380CDE-16#PBF Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
