My Inquiry
My Account
Analog Devices Inc. LTC2380CDE-24#PBF
- Part No.:
- LTC2380CDE-24#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 16-WFDFN Exposed Pad
- Datasheet:
-
LTC2380CDE-24#PBF.pdf
- Description:
- IC ADC 24BIT SAR 16DFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,864
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2380CDE-24#PBF from Analog Devices (formerly Linear Technology) is a 24-bit, 2 Msps successive approximation register (SAR) analog-to-digital converter with integrated real-time digital averaging filter, ±VREF fully differential input (2.5V–5.1V reference), and single 2.5V analog supply. It delivers ±3.5 ppm INL max, 101 dB SNR at 1.5 Msps, and 145 dB dynamic range at 30.5 sps for high-precision data acquisition in seismology and medical imaging systems.
For engineers reviewing the LTC2380CDE-24#PBF datasheet, LTC2380CDE-24#PBF pinout, LTC2380CDE-24#PBF application, or LTC2380CDE-24#PBF equivalent, key selection considerations include its 16-lead 4 mm × 3 mm DFN package, guaranteed 24-bit no-missing-codes operation, SPI-compatible daisy-chain interface, digital gain compression (DGC) mode, and temperature-stable performance across 0°C to 70°C.
Technical Context
The LTC2380CDE-24#PBF implements a charge-redistribution SAR architecture with a 24-bit CDAC and differential comparator, sampling at up to 2 Msps with 343 ns conversion time. Its integrated digital filter supports real-time averaging of 1–65536 samples without configuration registers, enabling scalable dynamic range from 101 dB to 145 dB.
It features dual-supply operation: 2.375 V–2.625 V on VDD for analog core and 1.71 V–5.25 V on OVDD for SPI I/O, supporting 1.8 V/2.5 V/3.3 V/5 V logic levels. The REF/DGC pin selects between full-scale ±VREF mode or compressed 10%–90% range mode, while CHAIN pin enables daisy-chain serial data routing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 24-bit - guarantees no missing codes over full operating range |
| Max Sampling Rate | 2 Msps - supports high-speed transient capture with 343 ns conversion time |
| INL (max) | ±3.5 ppm - ensures <0.00035% full-scale linearity error in precision measurement |
| Dynamic Range | 145 dB at 30.5 sps - enables ultra-low-noise DC measurements (e.g., geophysical sensors) |
| Power Dissipation | 28 mW at 2 Msps - achieves low thermal load in dense PCB layouts |
| Reference Range | 2.5 V to 5.1 V - allows flexible signal scaling with external or internal reference sources |
| Operating Temp | 0°C to 70°C - rated for commercial-grade instrumentation and industrial control environments |
Pinout & Package
Package: 16-lead (4 mm × 3 mm) plastic DFN with exposed pad (Pin 17 = GND, must be soldered to PCB ground plane). Thermal resistance θJA = 40°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CHAIN (1) | Chain Mode Selector | High = daisy-chain mode (RDL/SDI becomes SDI); low = normal mode (RDL/SDI enables SDO bus) |
| VDD (2) | Analog Core Supply | 2.375 V–2.625 V; powers SAR core and reference buffer; requires 10 µF ceramic bypass |
| GND (3,6,10,16) | Analog/Digital Ground | Multiple ground pins minimize noise coupling; exposed pad (17) is mandatory GND connection |
| IN+, IN– (4,5) | Differential Analog Inputs | ±VREF fully differential range; 45 pF input capacitance in sample mode; 40 Ω switch RON |
| REF (7) | Reference Input | 2.5 V–5.1 V reference voltage; requires 47 µF X7R ceramic decoupling (1210 size) |
| REF/DGC (8) | Reference/Digital Gain Compression Control | Tied to REF = full-scale ±VREF; tied to GND = compressed 10%–90% range for improved SNR on small signals |
| CNV (9) | Convert Trigger | Rising edge initiates conversion and powers up ADC; auto-power-down between conversions |
| BUSY (11) | Conversion Status Indicator | High during conversion; used for timing synchronization or interrupt generation |
| RDL/SDI (12) | Bus Enable / Serial Data Input | In normal mode: controls SDO output enable; in chain mode: accepts daisy-chained data from upstream ADC |
| SCK (13) | Serial Clock Input | Supports up to 100 MHz clock (10 ns min period); MSB-first SPI-compatible interface |
| SDO (14) | Serial Data Output | 2's complement 24-bit output; Hi-Z when RDL/SDI is high in normal mode |
| OVDD (15) | I/O Interface Supply | 1.71 V–5.25 V; sets logic thresholds for all digital pins; bypass with 0.1 µF capacitor |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Digital Averaging Filter | Real-time averaging of 1–65536 samples without registers or firmware overhead, enabling selectable dynamic range |
| Digital Gain Compression (DGC) | Configurable full-scale definition via REF/DGC pin-compresses input range to improve effective resolution on small signals |
| SPI-Compatible Daisy-Chain Mode | Enables synchronized multi-channel acquisition with minimal interconnect; eliminates separate control lines per device |
| Auto Power-Down Between Conversions | Reduces power dissipation at lower sampling rates-2.5 µW in power-down mode |
| 50 Hz / 60 Hz Rejection | Integrated digital filtering provides inherent line-frequency rejection without external notch filters |
Applications
| Seismology Data Acquisition | Energy Exploration Sensors |
|---|---|
Use Scenario: High-resolution digitization of low-amplitude seismic waveforms from geophone arrays deployed in boreholes or surface arrays. IC Role / Device Role / Timing Role: Primary 24-bit SAR ADC capturing broadband analog signals with 145 dB dynamic range at sub-100 sps for deep-earth signal analysis. Use Value: Enables detection of micro-tremors below –120 dBFS using real-time 65536-sample averaging, eliminating need for external DSP preprocessing. | Use Scenario: Signal conditioning and digitization in downhole logging tools measuring resistivity, gamma ray, and acoustic impedance in oil/gas wells. IC Role / Device Role / Timing Role: Precision ADC interfacing with low-noise front-end amplifiers and high-stability references in harsh 125°C-rated tool housings. Use Value: ±3.5 ppm INL and guaranteed no-missing-codes ensure traceable calibration over 20+ year field deployments without recalibration drift. |
| Medical Imaging Front-End | High-Speed Industrial DAQ |
Use Scenario: Digitizing analog outputs from ultrasound transducer beamformers or MRI gradient coil feedback sensors requiring ultra-low distortion. IC Role / Device Role / Timing Role: 24-bit SAR ADC providing 100 dB SNR and –117 dB THD at 2 kHz for artifact-free image reconstruction. Use Value: DGC mode improves effective resolution on weak echo returns, while SPI daisy-chain simplifies multi-channel probe head wiring. | Use Scenario: Real-time monitoring of motor current, vibration, and temperature in predictive maintenance systems with edge AI inference. IC Role / Device Role / Timing Role: High-speed 2 Msps ADC feeding time-series data to FPGA-based feature extraction engines. Use Value: 343 ns conversion time and BUSY-synchronized readout enable deterministic 500 ns sample-to-data latency for closed-loop control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-resolution SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS127L23IRHBT | 24-bit, 512 ksps delta-sigma ADC; higher resolution but lower speed; integrated PGA and reference; 3.3 V only | Better for DC-optimized systems (e.g., weigh scales); unsuitable for >1 Msps transient capture | Select if oversampling stability > speed; avoid if >1 Msps sampling required |
| AD7616BSTZ | 16-bit, 1 Msps dual simultaneous-sampling SAR ADC; no integrated digital filter; 5 V tolerant I/O; parallel + SPI interface | Higher channel count (16 ch) but lower resolution; suited for multi-sensor industrial PLCs | Select for cost-sensitive, multi-channel systems where 16-bit resolution suffices |
Compared with ADS127L23IRHBT and AD7616BSTZ, the LTC2380CDE-24#PBF uniquely balances 24-bit resolution, 2 Msps speed, and integrated real-time averaging-making it optimal for applications demanding both wide dynamic range and high temporal fidelity without external processing.
Availability
LTC2380CDE-24#PBF is available at Aetrix Electronics and suitable for seismology instrumentation, energy exploration sensor modules, and medical imaging front-ends requiring stable component supply, long-term lifecycle support, and guaranteed commercial-temperature performance.
Supply support for LTC2380CDE-24#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving precision instrumentation, industrial, automotive, and healthcare markets.
The LTC2380-24 product line was developed by Linear Technology (acquired by ADI in 2017) to address demand for ultra-high-resolution, low-power SAR ADCs with integrated digital post-processing-specifically targeting applications where external FPGA/DSP resources are constrained.
FAQ
What is the maximum sampling rate supported by the LTC2380CDE-24#PBF?
The LTC2380CDE-24#PBF supports a maximum sampling rate of 2 Msps, with a minimum conversion time of 343 ns. This is achievable under specified conditions: VDD = 2.5 V, OVDD ≥ 2.5 V, N ≥ 4 averages, and proper decoupling. At 1.5 Msps, the device achieves 101 dB SNR and 97.5 dB SINAD with VREF = 5 V and fIN = 2 kHz.
Does the LTC2380CDE-24#PBF require external configuration registers or software initialization?
No, the LTC2380CDE-24#PBF does not require external configuration registers or software initialization. Its integrated digital averaging filter operates automatically based on the number of averages (N = 1 to 65536) set via hardware pins or SPI command-no register writes are needed. The REF/DGC and CHAIN pins configure core functionality directly, eliminating firmware dependencies.
How does the REF/DGC pin affect the input range of the LTC2380CDE-24#PBF?
When the REF/DGC pin is tied to REF, the LTC2380CDE-24#PBF uses the full ±VREF differential input range. When tied to GND, it enables Digital Gain Compression (DGC), redefining full-scale to correspond to inputs spanning only 10% to 90% of ±VREF-effectively increasing resolution for small-signal measurements while maintaining 24-bit code width.
What package type and thermal characteristics apply to the LTC2380CDE-24#PBF?
The LTC2380CDE-24#PBF uses a 16-lead (4 mm × 3 mm) plastic DFN package with an exposed thermal pad (Pin 17 = GND). Its junction-to-ambient thermal resistance is θJA = 40°C/W. The exposed pad must be soldered to the PCB ground plane for both thermal performance and electrical integrity.
Is the LTC2380CDE-24#PBF compatible with 1.8 V digital interfaces?
Yes, the LTC2380CDE-24#PBF supports 1.8 V digital interfaces via its OVDD supply pin, which accepts 1.71 V to 5.25 V. All digital I/O pins (SCK, SDO, RDL/SDI, CNV, BUSY, CHAIN) are referenced to OVDD, enabling direct connection to 1.8 V FPGAs or microcontrollers without level shifters.
LTC2380CDE-24#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 24
- Sampling Rate (Per Second):
- 2M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- SPI
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- External
- Voltage - Supply, Analog:
- 1.71V ~ 5.25V
- Voltage - Supply, Digital:
- 1.71V ~ 5.25V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 16-DFN (4x3)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2380CDE-24#PBF FAQ
1.How can I place an order for LTC2380CDE-24#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2380CDE-24#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2380CDE-24#PBF reliable?
The price and inventory of LTC2380CDE-24#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2380CDE-24#PBF is usually 5 days.
3.What payment methods are accepted for LTC2380CDE-24#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2380CDE-24#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2380CDE-24#PBF?
LTC2380CDE-24#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2380CDE-24#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2380CDE-24#PBF?
For technical support, including LTC2380CDE-24#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2380CDE-24#PBF requirements.
6.How does Aetrix verify that LTC2380CDE-24#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2380CDE-24#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2380CDE-24#PBF meets industry standards.
7.What is the process for return or replacement of LTC2380CDE-24#PBF?
All LTC2380CDE-24#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2380CDE-24#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2380CDE-24#PBF part is unused and in its original packaging.
Return procedure for LTC2380CDE-24#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2380CDE-24#PBF Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
