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Analog Devices Inc. LTC2385CUH-18#PBF

Part No.:
LTC2385CUH-18#PBF
Manufacturer:
Analog Devices Inc.
Category:
Analog to Digital Converters (ADC)
Package:
32-WFQFN Exposed Pad
Datasheet:
AetrixLTC2385CUH-18#PBF.pdf
Description:
IC ADC 18BIT SAR 32QFN
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:4,624

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Product details

Overview

LTC2385CUH-18#PBF from Analog Devices (formerly Linear Technology) is an 18-bit, 5 Msps successive approximation register (SAR) analog-to-digital converter with serial LVDS interface, ±4.096 V differential input range, 95.7 dB SNR at 1 MHz, and internal 2.048 V reference. It delivers no pipeline delay, guaranteed 18-bit no-missing-codes performance, and operates from 5 V and dual 2.5 V supplies - ideal for high-speed imaging, instrumentation, and closed-loop control systems requiring precise wide-dynamic-range digitization.

For engineers reviewing the LTC2385CUH-18#PBF datasheet, LTC2385CUH-18#PBF pinout, LTC2385CUH-18#PBF application, or LTC2385CUH-18#PBF equivalent, key selection considerations include its 5 Msps throughput with zero-cycle latency, LVDS one/two-lane serial output flexibility, ±1.5 LSB INL max over temperature, 32-pin 5 mm × 5 mm QFN package, and integrated reference buffer supporting 4.096 V output.

Technical Context

The LTC2385CUH-18#PBF implements a true SAR architecture with no pipeline latency, enabling deterministic timing for real-time control loops. Its conversion cycle begins on a rising edge of the differential CNV+ signal and completes in ≤101 ns, with acquisition time defined relative to tCYC.

It features a fully differential analog front-end with 200 MHz –3 dB input bandwidth, CMRR ≥75 dB at 1 MHz, and supports both internal reference (2.048 V ±0.25%, ±20 ppm/°C) and external buffered reference modes. The LVDS digital interface operates at 5 Msps with configurable one-lane (18-bit serial) or two-lane (9-bit parallel per lane) output, synchronized to an externally supplied LVDS clock (CLK+/CLK–).

Key Specifications

Parameter Value and Actual Design Meaning
Resolution 18-bit, guaranteed no missing codes - ensures full dynamic range utilization without code gaps in precision measurement.
Sampling Rate 5 Msps maximum - enables Nyquist sampling up to 2.5 MHz input signals without aliasing.
SNR 95.7 dB (typ) at fIN = 1 MHz - supports >15.9 effective bits for high-fidelity signal capture in instrumentation.
INL ±1.5 LSB (max) over temperature - maintains linearity critical for calibration-sensitive applications like ATE and medical imaging.
Power Dissipation 78 mW at 5 Msps - balances high-speed performance with thermal manageability in dense PCB layouts.
Reference Internal 2.048 V ±0.25% initial accuracy, ±20 ppm/°C TC - eliminates need for external reference in cost- and space-constrained designs.
Digital Interface LVDS serial output with selectable one-lane or two-lane mode - reduces PCB trace count vs parallel interfaces while maintaining timing integrity.

Pinout & Package

Package: 32-lead (5 mm × 5 mm) plastic QFN (UH), exposed pad (Pin 33) connected to GND. Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.

Pin/Terminal Circuit Role Design Meaning
GND (Pins 1, 4, 10, 21, 26, 29) Ground reference Multiple dedicated ground pins minimize impedance and noise coupling; must connect to solid ground plane under device.
IN+, IN– (Pins 2, 3) Differential analog inputs Accept ±4.096 V differential swing with common-mode range centered at 2.048 V; require matched 180° out-of-phase drive.
REFGND (Pins 5, 6) Reference ground Isolated ground path for reference circuitry; shorted together and tied to exposed pad to reduce reference noise.
REFBUF (Pins 7, 8) Reference buffer output Provides 4.096 V (2× gain) buffered reference; bypassed with 10 µF ceramic capacitor to REFGND for stability.
REFIN (Pin 9) Internal reference output / external reference input Outputs 2.048 V internal reference; accepts external 2.008–2.088 V reference if higher accuracy required.
VDD (Pins 11, 12) 5 V analog supply Supplies core ADC and reference; requires 0.1 µF + 10 µF local decoupling to GND.
PD (Pin 13) Power-down enable Active-low input referenced to OVDD; reduces total current to 10 µW when asserted.
TESTPAT (Pin 14) LVDS test pattern enable Forces known data pattern on DA/DB outputs - used for interface validation and system debug.
DA+, DA– (Pins 17, 18) LVDS data output lane A Primary serial data output in one-lane mode; carries all 18 bits sequentially; active in both one- and two-lane modes.
DCO+, DCO– (Pins 19, 20) LVDS data clock output Echoes CLK+/CLK– with minimal skew; used by FPGA/ASIC to latch DA/DB data reliably.
OVDD (Pin 22) 2.5 V output supply Powers LVDS drivers (DA/DB/DCO); requires 0.1 µF decoupling to GND.
CLK+, CLK– (Pins 23, 24) LVDS clock input External master clock (5 MHz nominal) that controls conversion timing and data serialization rate.
TWOLANES (Pin 25) Two-lane mode select High = two-lane mode (9 bits per lane on DA/DB); low = one-lane mode (18 bits on DA only); referenced to VDDL.
CNV+, CNV– (Pins 27, 28) Differential conversion start Rising edge initiates sample-and-hold hold phase and conversion; supports single-ended CNV+ (CNV– = GND) with 2.5 V CMOS logic.
VDDL (Pins 30, 31) 2.5 V logic supply Powers digital control logic (CNV, PD, TWOLANES, TESTPAT); requires 0.1 µF + 10 µF decoupling to GND.
VCM (Pin 32) Common-mode output Provides 2.048 V bias for external driver circuits; optional - bypass with 0.1 µF if used.
Exposed Pad (Pin 33) Thermal & electrical ground Mandatory connection to PCB ground plane via multiple vias - essential for thermal dissipation and noise reduction.

Key Features

Feature Design Value
No pipeline latency Enables deterministic real-time control loop closure with sub-100 ns conversion-to-data-ready timing (tCONV ≤ 101 ns).
Integrated 2.048 V reference Eliminates external reference component count and layout area; ±20 ppm/°C TC ensures stable performance across 0°C to 70°C operating range.
LVDS serial interface Reduces pin count and EMI vs parallel interfaces; supports flexible one- or two-lane configuration to match FPGA/ASIC I/O constraints.
±1.5 LSB INL (max) Ensures monotonicity and accurate transfer function fidelity - critical for calibration-critical applications like spectral analysis and metrology.
78 mW power at 5 Msps Delivers high-speed performance with low thermal load - suitable for compact, fanless embedded systems and portable instrumentation.
32-pin 5 mm × 5 mm QFN Enables high-density PCB layouts while maintaining manufacturability and thermal performance via exposed pad grounding.

Applications

High-Speed Imaging Automated Test Equipment (ATE)

Use Scenario: Digitizing fast-rising transient waveforms from CCD/CMOS sensors or pulsed laser receivers in medical ultrasound or industrial inspection systems.

IC Role / Device Role / Timing Role: Primary SAR ADC capturing 18-bit samples at 5 Msps with zero-latency operation to preserve signal timing integrity.

Use Value: 95.7 dB SNR and 101 dB SFDR at 1 MHz enable detection of low-amplitude features buried in noise, improving image contrast resolution.

Use Scenario: High-accuracy voltage/current measurement in semiconductor parametric testers and board-level functional testers.

IC Role / Device Role / Timing Role: Precision digitizer for DC and AC stimulus-response characterization, leveraging guaranteed no-missing-codes and ±1.5 LSB INL.

Use Value: Internal 2.048 V reference with ±0.25% initial accuracy reduces calibration overhead and improves test repeatability across production batches.

Real-Time Control Loops Communications Signal Analysis

Use Scenario: Closed-loop feedback in motor drives, RF power amplifiers, or adaptive optics where sub-microsecond decision latency is mandatory.

IC Role / Device Role / Timing Role: Low-latency ADC providing immediate conversion results to FPGA-based PID controllers without pipeline delay.

Use Value: Deterministic tCONV ≤ 101 ns and no cycle latency allow control updates every 200 ns - enabling kHz-bandwidth servo response.

Use Scenario: Wideband IF sampling in software-defined radio (SDR) receivers and spectrum analyzers requiring >100 dB spurious-free dynamic range.

IC Role / Device Role / Timing Role: High-SFDR digitizer capturing multi-MHz bandwidth signals with minimal harmonic distortion (THD = –100 dB at 1 MHz).

Use Value: 200 MHz –3 dB input bandwidth and 101 dB SFDR support clean digitization of complex modulated waveforms up to 2.5 MHz Nyquist frequency.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed SAR ADC applications.

Alternative Part Technical Difference Application Difference Selection Advice
AD7960BCPZ-RL7 18-bit, 5 Msps SAR ADC with SPI interface; requires external reference; 91.5 dB SNR (typ); 33 mW power. Lacks LVDS interface and internal reference - demands additional reference IC and level-shifting for high-speed FPGA interfacing. Select when SPI compatibility, lower power, or external reference flexibility outweighs need for integrated timing and reduced layout complexity.
ADS8860IPWR 16-bit, 1 Msps SAR ADC with SPI interface; internal reference; 92 dB SNR (typ); 10 mW power. Lower resolution and speed; no LVDS; smaller 16-pin WQFN package - suited for portable or battery-powered instrumentation. Select when 16-bit resolution suffices and ultra-low power or compact size is prioritized over 5 Msps throughput and 18-bit fidelity.

Compared with AD7960BCPZ-RL7 and ADS8860IPWR, the LTC2385CUH-18#PBF uniquely combines 18-bit resolution, 5 Msps speed, integrated LVDS interface, and internal reference in a single 32-pin QFN - reducing BOM count, layout risk, and timing design effort for high-performance data acquisition systems.

Availability

LTC2385CUH-18#PBF is available at Aetrix Electronics and suitable for high-speed imaging, automated test equipment, real-time control loops, and communications signal analysis requiring stable component supply and long-term design-in support.

Supply support for LTC2385CUH-18#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2385CUH-18#PBF belongs to ADI's high-speed precision SAR ADC product line, designed specifically for applications demanding zero-latency, wide dynamic range, and robust serial interfacing - such as next-generation test instrumentation and real-time embedded control systems.

FAQ

What is the operating temperature range for the LTC2385CUH-18#PBF?

The LTC2385CUH-18#PBF is specified for operation from 0°C to 70°C (Commercial grade). This range is confirmed in the "ORDER INFORMATION" table of the datasheet, where "C" denotes the commercial temperature grade. The part uses the UH (32-lead QFN) package and carries the #PBF suffix indicating lead-free finish.

Does the LTC2385CUH-18#PBF require an external reference?

No, the LTC2385CUH-18#PBF includes an internal 2.048 V reference with ±0.25% initial accuracy and ±20 ppm/°C temperature coefficient. It also integrates a 2× gain reference buffer delivering 4.096 V on REFBUF pins. An external reference may be applied to REFIN only if higher accuracy or different voltage is needed - otherwise, the internal reference is fully functional and recommended for simplified design.

How does the LVDS interface of the LTC2385CUH-18#PBF operate in one-lane versus two-lane mode?

In one-lane mode (TWOLANES = low), the LTC2385CUH-18#PBF outputs all 18 bits sequentially on DA+/DA–, while DB+/DB– drivers are disabled to save power. In two-lane mode (TWOLANES = high), it outputs odd bits (D17, D15,…D1) on DA+/DA– and even bits (D16, D14,…D0) on DB+/DB– simultaneously - halving the LVDS bit rate and easing timing closure on high-speed FPGAs.

What is the absolute maximum input voltage range for IN+ and IN– on the LTC2385CUH-18#PBF?

The absolute maximum analog input voltage range for IN+ and IN– is (GND – 0.3 V) to (VDD + 0.3 V), per the Absolute Maximum Ratings table. However, the functional differential input range is ±4.096 V (i.e., IN+ – IN– = ±4.096 V), with common-mode voltage constrained to VREFBUF/2 ± 0.1 V (≈2.048 V ± 0.1 V). Exceeding these functional limits degrades linearity and may cause measurement errors.

Can the LTC2385CUH-18#PBF be used with a single-ended CNV signal?

Yes, the LTC2385CUH-18#PBF supports single-ended conversion start: tie CNV– to GND and drive CNV+ with a 2.5 V CMOS signal (VIH ≥ 1.7 V, VIL ≤ 0.6 V, referenced to VDDL). This is explicitly documented in the "DIGITAL INPUTS AND DIGITAL OUTPUTS" section and simplifies interface design when differential clock resources are limited.

LTC2385CUH-18#PBF Specifications

Product attributes
Attribute value
Manufacturer:
Analog Devices Inc.
Series:
-
Package/Case:
32-WFQFN Exposed Pad
Packaging:
Tube
Product Status:
Active
Number of Bits:
18
Sampling Rate (Per Second):
5M
Number of Inputs:
1
Input Type:
Differential
Data Interface:
LVDS - Serial
Configuration:
S/H-ADC
Ratio - S/H:ADC:
1:1
Number of A/D Converters:
1
Architecture:
SAR
Reference Type:
External, Internal
Voltage - Supply, Analog:
5V
Voltage - Supply, Digital:
2.375V ~ 2.625V
Features:
-
Operating Temperature:
0°C ~ 70°C
Supplier Device Package:
32-QFN (5x5)
Mounting Type:
Surface Mount
Grade:
-
Qualification:
-

LTC2385CUH-18#PBF FAQ

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Please submit a Request for Quotation (RFQ) for LTC2385CUH-18#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

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The price and inventory of LTC2385CUH-18#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2385CUH-18#PBF is usually 5 days.

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LTC2385CUH-18#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LTC2385CUH-18#PBF order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LTC2385CUH-18#PBF?

For technical support, including LTC2385CUH-18#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2385CUH-18#PBF requirements.

6.How does Aetrix verify that LTC2385CUH-18#PBF is sourced from the original manufacturer or authorized distributors?

All LTC2385CUH-18#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2385CUH-18#PBF meets industry standards.

7.What is the process for return or replacement of LTC2385CUH-18#PBF?

All LTC2385CUH-18#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2385CUH-18#PBF, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LTC2385CUH-18#PBF part is unused and in its original packaging.

Return procedure for LTC2385CUH-18#PBF:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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