Analog Devices Inc. LTC2385IUH-16#PBF

Overview

LTC2385IUH-16#PBF from Analog Devices (formerly Linear Technology) is a 16-bit, 5 Msps successive approximation register (SAR) analog-to-digital converter with serial LVDS interface, ±0.5 LSB INL (max), 93.8 dB SNR at 1 MHz input, and 78 mW power dissipation. It operates from 5 V and dual 2.5 V supplies, features an internal 2.048 V reference with ±20 ppm/°C tempco, and targets high-speed imaging, instrumentation, and control-loop applications.

For engineers reviewing the LTC2385IUH-16#PBF datasheet, LTC2385IUH-16#PBF pinout, LTC2385IUH-16#PBF application, or LTC2385IUH-16#PBF equivalent, key selection considerations include no-pipeline-delay operation, differential LVDS data output timing (one- or two-lane mode), guaranteed 16-bit no-missing-codes performance, and support for Nyquist sampling up to 2.5 MHz input frequency.

Technical Context

The LTC2385IUH-16#PBF implements a true SAR architecture with zero-cycle latency-conversion completes before the next sample begins-enabling deterministic timing in closed-loop systems. Its internal 2× gain reference buffer delivers 4.096 V (±0.15 LSB full-scale error), and the analog front-end supports ±4.096 V differential input range with 200 MHz –3 dB bandwidth.

Timing is synchronized via LVDS clock inputs (CLK+/CLK–), with conversion start triggered by differential CNV+/CNV– or single-ended CNV+ (CNV– tied to GND). Output data is serialized over LVDS lanes (DA+/DA–, DB+/DB–) with DCO+/DCO– providing a phase-aligned echo clock for latch synchronization.

Key Specifications

Pinout & Package

Package: 32-lead (5 mm × 5 mm) plastic QFN (UH package); exposed pad (Pin 33) must be soldered to PCB ground plane.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed SAR ADC applications.

Compared with AD9269BCPZ-20 and ADS8860IRGET, the LTC2385IUH-16#PBF uniquely balances 5 Msps speed, LVDS serialization, on-chip reference, and sub-100 mW power - making it optimal for space-constrained, medium-throughput systems requiring deterministic timing and minimal external components.

Availability

LTC2385IUH-16#PBF is available at Aetrix Electronics and suitable for high-speed imaging, industrial control loops, and communications receiver designs requiring stable component supply, long-term manufacturability, and guaranteed extended temperature operation (–40°C to +85°C).

Supply support for LTC2385IUH-16#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.

The LTC2385IUH-16#PBF belongs to ADI's high-speed precision SAR ADC product line, engineered for applications demanding both speed (≥5 Msps) and DC/AC accuracy (≤±0.5 LSB INL, ≥93 dB SNR) without pipeline latency.

FAQ

What is the operating temperature range for the LTC2385IUH-16#PBF?

The LTC2385IUH-16#PBF is rated for industrial temperature operation from –40°C to +85°C, as indicated by the "I" grade in the part number. This is confirmed in the Absolute Maximum Ratings table and Electrical Characteristics section, where all "l"-marked specifications apply across this full range.

Does the LTC2385IUH-16#PBF require an external reference?

No, the LTC2385IUH-16#PBF includes an internal 2.048 V reference with ±20 ppm/°C max temperature coefficient and a 2× gain reference buffer delivering 4.096 V. An external reference may be applied to REFIN only if higher initial accuracy or lower drift is required - the internal reference is fully functional and calibrated for standard use of the LTC2385IUH-16#PBF.

How does the LVDS interface of the LTC2385IUH-16#PBF operate in one-lane versus two-lane mode?

In one-lane mode (TWOLANES = low), the LTC2385IUH-16#PBF serializes all 16 bits on DA+/DA– at 80 MSPS (16 bits × 5 Msps). In two-lane mode (TWOLANES = high), it outputs 8 bits on DA+/DA– and 8 bits on DB+/DB– simultaneously at 40 MSPS per lane. DCO+/DCO– provides a phase-aligned echo clock for synchronous latching in both modes.

What is the significance of "no pipeline delay" in the LTC2385IUH-16#PBF?

"No pipeline delay" means the LTC2385IUH-16#PBF is a true successive approximation register (SAR) ADC - its conversion result is available immediately after t_CONV (max 101 ns), with no queued samples or internal FIFO. This enables deterministic, cycle-accurate timing essential for real-time control loops, where delayed data would destabilize feedback response - a key differentiator from pipelined or sigma-delta ADCs.

Can the LTC2385IUH-16#PBF be powered down to reduce system power consumption?

Yes, asserting PD (Pin 13) low places the LTC2385IUH-16#PBF into power-down mode, reducing total supply current to 10 μA and power dissipation to 10 μW. All circuitry - including the LVDS interface and reference buffer - is disabled. Recovery time is specified in the datasheet timing diagram, and normal operation resumes within nanoseconds after PD is returned high.