Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Analog Devices Inc. LTC2386IUH-18#PBF

Name: LTC2386IUH-18#PBF
Brand: Analog Devices Inc.
SKU: LTC2386IUH-18#PBF
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: LTC2386IUH-18#PBF

Manufacturer:: Analog Devices Inc.

Category:: Analog to Digital Converters (ADC)

Package:: 32-WFQFN Exposed Pad

Datasheet:: LTC2386IUH-18#PBF.pdf

Description:: IC ADC 18BIT SAR 32QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:609

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

LTC2386IUH-18#PBF from Analog Devices (formerly Linear Technology) is an 18-bit, 10 Msps successive approximation register (SAR) analog-to-digital converter with serial LVDS interface, ±4.096 V differential input range, ±1.75 LSB max INL, and 95.7 dB SNR at 1 MHz input - designed for high-speed imaging, instrumentation, and control-loop acquisition systems.

For engineers reviewing the LTC2386IUH-18#PBF datasheet, LTC2386IUH-18#PBF pinout, LTC2386IUH-18#PBF application, or LTC2386IUH-18#PBF equivalent, key selection criteria include no pipeline latency, guaranteed 18-bit no-missing-codes operation, internal 2.048 V reference with ±20 ppm/°C max drift, 32-pin 5 mm × 5 mm QFN package, and dual-mode LVDS output (one- or two-lane).

Technical Context

The LTC2386IUH-18#PBF implements a true SAR architecture with zero-cycle latency and no pipeline delay, enabling deterministic timing for closed-loop feedback. Its fully differential front-end accepts ±4.096 V inputs referenced to 2.048 V common mode, with 200 MHz –3 dB input bandwidth and 75 dB CMRR at 1 MHz.

It integrates a precision 2.048 V bandgap reference (±0.25% initial accuracy), a 2× gain reference buffer (4.096 V output), and a high-speed serial LVDS interface supporting both one-lane (18-bit serial) and two-lane (9-bit parallel per lane) data output modes - configurable via the TWOLANES pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	18-bit, guaranteed no missing codes - ensures full dynamic range utilization without code gaps in critical measurement applications.
Sampling Rate	10 Msps maximum - supports Nyquist sampling of up to 5 MHz input signals without aliasing.
SNR / SINAD	95.7 dB / 94.6 dB typical at f_IN = 1 MHz - enables >15.5 effective number of bits (ENOB) for high-fidelity signal capture.
INL / DNL	±1.75 LSB max INL, ±0.9 LSB max DNL - maintains linearity across full scale for precision metrology and calibration systems.
Power Dissipation	97 mW at 10 Msps, 10 μW in power-down - balances high-speed performance with thermal management in dense PCB layouts.
Reference	Internal 2.048 V reference (±20 ppm/°C max TC), buffered to 4.096 V - eliminates need for external reference in most applications while ensuring stable scaling.
Digital Interface	LVDS serial output with selectable one- or two-lane mode - reduces PCB trace count vs parallel interfaces while maintaining noise immunity and timing margin.

Pinout & Package

Package: 32-lead (5 mm × 5 mm) plastic QFN (UH package) with exposed pad (Pin 33) soldered to PCB ground plane. Thermal resistance θ_JA = 34 °C/W.

Pin/Terminal	Circuit Role	Design Meaning
GND (Pins 1, 4, 10, 21, 26, 29)	Ground reference	Multiple low-inductance ground connections required for analog, digital, and reference domains to minimize noise coupling.
IN+, IN– (Pins 2, 3)	Differential analog inputs	Accept ±4.096 V differential swing centered at 2.048 V common mode; require matched 180° out-of-phase drive.
REFGND (Pins 5, 6)	Reference ground	Must be shorted together and connected directly to exposed pad and reference bypass capacitors - forms dedicated low-noise reference return path.
REFBUF (Pins 7, 8)	Buffered reference output	Provides 4.096 V (2× internal reference); bypassed with 10 µF ceramic capacitor to REFGND for stability and noise rejection.
REFIN (Pin 9)	Internal reference output / external reference input	Outputs 2.048 V; accepts external 2.008–2.088 V reference if higher accuracy is needed; tie to GND to disable internal buffer.
VDD (Pins 11, 12)	5 V analog supply	4.75–5.25 V range; requires local 0.1 µF + 10 µF ceramic decoupling to GND for ADC core stability.
PD (Pin 13)	Power-down control	Active-low digital input (OVDD-referenced); asserts 10 µW shutdown state when logic low - critical for duty-cycled systems.
CLK+/CLK– (Pins 23, 24)	LVDS clock input	Accepts external LVDS clock (175–650 mV differential swing); defines sampling instant and serial data timing.
DA+/DA–, DB+/DB– (Pins 15–18)	LVDS data outputs	In one-lane mode: DA± carries full 18-bit serial stream; DB± disabled. In two-lane mode: DA± and DB± each carry 9-bit nibbles synchronously.
CNV+/CNV– (Pins 27, 28)	Conversion start trigger	Differential LVDS input (175–650 mV VID); rising edge initiates sample-and-hold hold phase - supports precise timing control in synchronous systems.

Key Features

Feature	Design Value
No pipeline latency	Zero-cycle conversion delay enables real-time feedback in servo loops and adaptive control systems without timing compensation.
Internal 2.048 V reference	Guaranteed ±0.25% initial accuracy and ±20 ppm/°C max drift - eliminates external reference component count and layout complexity in portable or space-constrained designs.
Two-mode LVDS interface	Selectable one- or two-lane output via TWOLANES pin - allows trade-off between PCB routing density (one-lane) and reduced serialization clock frequency (two-lane).
High CMRR & low distortion	75 dB CMRR at 1 MHz and –101 dB THD at 1 MHz input - preserves signal integrity in noisy industrial or RF-adjacent environments.
Robust analog input structure	Input ESD protection diodes + 10 Ω series resistors + 18 pF sampling capacitance - withstands transient overvoltage while maintaining 200 MHz bandwidth and low charge kickback.

Applications

High-Speed Imaging Systems	Automated Test Equipment (ATE)
Use Scenario: Digitizing fast-rising X-ray detector pulses or laser interferometry signals in medical CT or semiconductor wafer inspection. IC Role / Device Role / Timing Role: Primary high-resolution digitizer capturing transient analog waveforms with deterministic 100 ns inter-sample timing and no latency-induced phase error. Use Value: 95.7 dB SNR and ±1.75 LSB INL ensure sub-0.003% amplitude fidelity across 18-bit dynamic range, critical for quantitative image reconstruction.	Use Scenario: High-throughput parametric testing of analog ICs requiring simultaneous multi-channel voltage/current measurement at 10 Msps. IC Role / Device Role / Timing Role: Precision acquisition engine synchronized to system test clock via LVDS CLK+/CLK–, delivering time-aligned 18-bit samples to FPGA-based analysis logic. Use Value: Guaranteed no-missing-codes operation and 102 dB SFDR at 1 MHz enable accurate characterization of device nonlinearities and harmonic content.
Real-Time Control Loops	Communications Signal Analysis
Use Scenario: Closed-loop motor control or RF power amplifier envelope tracking where ADC output must feed PID computation within one sample period. IC Role / Device Role / Timing Role: Latency-free SAR ADC providing immediate 18-bit result after CNV+ edge - eliminates pipeline delay compensation in firmware or hardware. Use Value: Deterministic t_CONV = 72 ns max ensures predictable loop timing budget, enabling >100 kHz control bandwidth without jitter-induced instability.	Use Scenario: Wideband spectrum monitoring or software-defined radio (SDR) front-end digitizing IF signals up to 5 MHz bandwidth. IC Role / Device Role / Timing Role: High-dynamic-range digitizer capturing modulated carriers with minimal quantization noise and spurious content. Use Value: 102 dB SFDR at 1 MHz and –83 dB THD at 5 MHz support clean demodulation of QAM-256 or OFDM signals in crowded spectral environments.

High-Speed Imaging Systems

Automated Test Equipment (ATE)

Use Scenario: Digitizing fast-rising X-ray detector pulses or laser interferometry signals in medical CT or semiconductor wafer inspection.

IC Role / Device Role / Timing Role: Primary high-resolution digitizer capturing transient analog waveforms with deterministic 100 ns inter-sample timing and no latency-induced phase error.

Use Value: 95.7 dB SNR and ±1.75 LSB INL ensure sub-0.003% amplitude fidelity across 18-bit dynamic range, critical for quantitative image reconstruction.

Use Scenario: High-throughput parametric testing of analog ICs requiring simultaneous multi-channel voltage/current measurement at 10 Msps.

IC Role / Device Role / Timing Role: Precision acquisition engine synchronized to system test clock via LVDS CLK+/CLK–, delivering time-aligned 18-bit samples to FPGA-based analysis logic.

Use Value: Guaranteed no-missing-codes operation and 102 dB SFDR at 1 MHz enable accurate characterization of device nonlinearities and harmonic content.

Real-Time Control Loops

Communications Signal Analysis

Use Scenario: Closed-loop motor control or RF power amplifier envelope tracking where ADC output must feed PID computation within one sample period.

IC Role / Device Role / Timing Role: Latency-free SAR ADC providing immediate 18-bit result after CNV+ edge - eliminates pipeline delay compensation in firmware or hardware.

Use Value: Deterministic t_CONV = 72 ns max ensures predictable loop timing budget, enabling >100 kHz control bandwidth without jitter-induced instability.

Use Scenario: Wideband spectrum monitoring or software-defined radio (SDR) front-end digitizing IF signals up to 5 MHz bandwidth.

IC Role / Device Role / Timing Role: High-dynamic-range digitizer capturing modulated carriers with minimal quantization noise and spurious content.

Use Value: 102 dB SFDR at 1 MHz and –83 dB THD at 5 MHz support clean demodulation of QAM-256 or OFDM signals in crowded spectral environments.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed SAR ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADS8860IRGET	16-bit, 1 Msps, SPI interface, single-ended input, no internal reference - lower resolution, slower, simpler interface.	Suitable for lower-bandwidth sensor readout or portable data loggers where size and power dominate over dynamic range.	Choose ADS8860IRGET only when 16-bit resolution and <1 Msps throughput meet system requirements and LVDS noise immunity is unnecessary.
AD7641ASTZ	18-bit, 2 Msps, parallel CMOS interface, ±5 V input, external reference required - slower, wider bus, no integrated reference.	Fits legacy systems with parallel data buses and existing ±5 V analog signal chains; requires external 5 V reference and more PCB area.	Choose AD7641ASTZ when migrating from older parallel-interface ADCs and board layout cannot accommodate LVDS routing constraints.

Compared with ADS8860IRGET and AD7641ASTZ, the LTC2386IUH-18#PBF uniquely delivers 10 Msps 18-bit performance with integrated reference and LVDS interface - enabling higher bandwidth, better noise immunity, and smaller footprint in next-generation test, imaging, and control systems.

Availability

LTC2386IUH-18#PBF is available at Aetrix Electronics and suitable for high-speed imaging, automated test equipment, real-time control loops, and communications signal analysis requiring stable component supply across extended temperature ranges.

Supply support for LTC2386IUH-18#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.

The LTC2386IUH-18#PBF belongs to Analog Devices' high-speed precision SAR ADC product line, engineered for applications demanding wide dynamic range, zero-latency operation, and robust serial interfacing in thermally constrained or noise-sensitive environments.

FAQ

What is the operating temperature range of the LTC2386IUH-18#PBF?

The LTC2386IUH-18#PBF is rated for –40°C to +85°C operation (Industrial grade). This extended range supports deployment in harsh environments such as factory automation controllers, outdoor test instrumentation, and base station monitoring systems where ambient temperatures exceed commercial limits. The part maintains full specification compliance-including ±1.75 LSB INL and 95.7 dB SNR-across this entire range.

Does the LTC2386IUH-18#PBF require an external reference?

No, the LTC2386IUH-18#PBF includes a precision internal 2.048 V reference with ±0.25% initial accuracy and ±20 ppm/°C max temperature coefficient, plus a 2× gain reference buffer delivering 4.096 V. An external reference is optional and only needed when higher absolute accuracy or lower drift is required; in that case, apply 2.008–2.088 V to REFIN while disabling the internal buffer by grounding REFIN.

How does the LVDS interface of the LTC2386IUH-18#PBF operate in one-lane versus two-lane mode?

In one-lane mode (TWOLANES = low), the LTC2386IUH-18#PBF outputs all 18 bits serially on DA+/DA– at 180 MHz (10 Msps × 18 bits), with DCO+/DCO– providing a phase-aligned echo of CLK+/CLK– for latch timing. In two-lane mode (TWOLANES = high), it outputs 9-bit nibbles simultaneously on DA+/DA– and DB+/DB– at 90 MHz, halving the required clock frequency and easing timing closure on dense PCBs.

What is the significance of "no pipeline delay" in the LTC2386IUH-18#PBF?

"No pipeline delay" means the LTC2386IUH-18#PBF is a true successive approximation register (SAR) ADC-not a pipelined or sigma-delta type-so its output corresponds deterministically to the analog input sampled at the CNV+ edge, with no additional clock cycles of latency. This enables immediate use of conversion results in time-critical control algorithms without predictive compensation or buffer management overhead.

Can the LTC2386IUH-18#PBF be used with single-ended input signals?

No-the LTC2386IUH-18#PBF is strictly a fully differential input ADC. Its IN+ and IN– pins must be driven 180° out-of-phase with a common mode voltage of 2.048 V ± 0.1 V. Single-ended signals require external differential driver circuitry (e.g., transformer or high-speed differential amplifier) to meet the specified input common-mode and differential swing requirements of ±4.096 V.

LTC2386IUH-18#PBF Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 32-WFQFN Exposed Pad

Packaging:: Tube

Product Status:: Active

Number of Bits:: 18

Sampling Rate (Per Second):: 10M

Number of Inputs:: 1

Input Type:: Differential

Data Interface:: LVDS - Serial

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: SAR

Reference Type:: External, Internal

Voltage - Supply, Analog:: 2.375V ~ 2.625V, 5V

Voltage - Supply, Digital:: 2.375V ~ 2.625V, 5V

Features:: -

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 32-QFN (5x5)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

LTC2386IUH-18#PBF FAQ

1.How can I place an order for LTC2386IUH-18#PBF through Aetrix?

Please submit a Request for Quotation (RFQ) for LTC2386IUH-18#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LTC2386IUH-18#PBF reliable?

The price and inventory of LTC2386IUH-18#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2386IUH-18#PBF is usually 5 days.

3.What payment methods are accepted for LTC2386IUH-18#PBF?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2386IUH-18#PBF transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for LTC2386IUH-18#PBF?

LTC2386IUH-18#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LTC2386IUH-18#PBF order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LTC2386IUH-18#PBF?

For technical support, including LTC2386IUH-18#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2386IUH-18#PBF requirements.

6.How does Aetrix verify that LTC2386IUH-18#PBF is sourced from the original manufacturer or authorized distributors?

All LTC2386IUH-18#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2386IUH-18#PBF meets industry standards.

7.What is the process for return or replacement of LTC2386IUH-18#PBF?

All LTC2386IUH-18#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2386IUH-18#PBF, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LTC2386IUH-18#PBF part is unused and in its original packaging.

Return procedure for LTC2386IUH-18#PBF:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…