My Inquiry
My Account
Analog Devices Inc. LTC2387IUH-18#PBF
- Part No.:
- LTC2387IUH-18#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LTC2387IUH-18#PBF.pdf
- Description:
- IC ADC 18BIT SAR 32QFN
- Quantity:
- Payment:
- Shipping:
Inventory:351
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2387IUH-18#PBF from Analog Devices (formerly Linear Technology) is an 18-bit, 15 Msps successive approximation register (SAR) analog-to-digital converter with serial LVDS interface, ±4.096 V differential input range, 95.7 dB SNR (typical at 1 MHz), and –40°C to +85°C industrial temperature rating. It delivers no pipeline delay, guaranteed 18-bit no-missing-codes performance, and is deployed in high-speed imaging, instrumentation, and closed-loop control systems requiring precise wide-dynamic-range digitization.
For engineers reviewing the LTC2387IUH-18#PBF datasheet, LTC2387IUH-18#PBF pinout, LTC2387IUH-18#PBF application, or LTC2387IUH-18#PBF equivalent, key selection criteria include its 15 Msps throughput with zero cycle latency, LVDS one/two-lane interface flexibility, internal 2.048 V reference with ±20 ppm/°C max drift, 32-pin 5 mm × 5 mm QFN package, and 125 mW power dissipation at full speed.
Technical Context
The LTC2387IUH-18#PBF implements a true SAR architecture-no pipeline stages, no inherent latency-enabling deterministic timing for real-time control loops. Its differential sampling circuitry accepts ±4.096 V inputs referenced to 2.048 V common mode, with 200 MHz –3 dB input bandwidth and 75 dB CMRR at 1 MHz.
Conversion is triggered by LVDS or CMOS-compatible CNV+ edge; output data is serialized via LVDS DA+/DA– (and DB+/DB– in two-lane mode) with DCO+ as echoed clock. Internal 2× reference buffer provides 4.096 V output, while REFIN supports external reference injection or internal reference disable.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 18-bit, guaranteed no missing codes - ensures full dynamic range utilization without code gaps in precision measurement. |
| Sampling Rate | 15 Msps - enables Nyquist sampling up to 7.5 MHz input signals, suitable for ultrasound, radar, and broadband test equipment. |
| SNR / SINAD | 95.7 dB / 95.7 dB (typ, fIN = 1 MHz) - supports >15.9 effective bits, critical for high-fidelity signal capture in spectral analysis. |
| INL / DNL | ±3 LSB max INL, ±0.9 LSB max DNL - maintains linearity across full scale for accurate DC and low-frequency measurements. |
| Reference | Internal 2.048 V bandgap reference, ±20 ppm/°C max TC - eliminates need for external reference in many industrial applications. |
| Power | 125 mW at 15 Msps, 10 μW in power-down - balances high-speed performance with thermal manageability in compact layouts. |
| Digital Interface | LVDS serial output (one- or two-lane), 1.25 ns CLK duty cycle - reduces pin count vs parallel interfaces while maintaining signal integrity at high data rates. |
Pinout & Package
Package: 32-lead (5 mm × 5 mm) plastic QFN (UH), exposed pad (Pin 33) connected to GND. Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pins 1, 4, 10, 21, 26, 29) | Ground reference | Multiple dedicated ground pins minimize ground bounce; must connect to solid PCB ground plane beneath device. |
| IN+, IN– (Pins 2, 3) | Differential analog input | Accepts ±4.096 V differential swing centered at 2.048 V common mode; requires matched 180° out-of-phase drive. |
| REFGND (Pins 5, 6) | Reference ground | Separate ground return for reference circuitry; shorted together and tied to exposed pad for optimal noise rejection. |
| REFBUF (Pins 7, 8) | 2× reference buffer output | Provides 4.096 V buffered reference; bypassed with 10 µF ceramic capacitor to REFGND for stability. |
| REFIN (Pin 9) | Internal reference output / external reference input | Outputs 2.048 V internal reference; accepts external 2.008–2.088 V reference if higher accuracy required. |
| VDD (Pins 11, 12) | 5 V analog supply | 4.75–5.25 V range; bypassed with 0.1 µF + 10 µF ceramics to suppress switching noise. |
| PD (Pin 13) | Power-down enable | Active-low digital input (OVDD-referenced); reduces total current to 10 µW when asserted. |
| CLK+, CLK– (Pins 23, 24) | LVDS clock input | Accepts 15 MHz LVDS clock; differential input voltage 175–650 mV with 0.8–1.7 V common mode. |
| CNV+, CNV– (Pins 27, 28) | LVDS conversion start | Rising edge on CNV+ initiates sample-and-hold hold phase; supports single-ended CNV+ (CNV– = GND) mode. |
| DA+, DA– (Pins 17, 18) | LVDS data output lane A | Primary serial data output; carries all 18 bits in one-lane mode, MSB-first, two's complement format. |
| DB+, DB– (Pins 15, 16) | LVDS data output lane B | Active only in two-lane mode; outputs even/odd bit pairs concurrently with DA+/DA– to halve data rate per lane. |
| DCO+, DCO– (Pins 19, 20) | LVDS data clock output | Echoed version of input CLK; used to latch DA/DB data at receiver, minimizing skew sensitivity. |
Key Features
| Feature | Design Value |
|---|---|
| No pipeline latency | Zero-cycle conversion delay enables deterministic timing for real-time feedback control loops without FIFO buffering. |
| LVDS serial interface | Reduces I/O count to 8 pins (vs 24+ for parallel), minimizes EMI, and supports PCB trace lengths >15 cm at 15 Msps. |
| Internal 2.048 V reference | Eliminates external reference component cost and layout area; ±0.25% initial accuracy and ±20 ppm/°C TC meet industrial calibration requirements. |
| Two-lane output mode | Halves LVDS data rate per lane (from 300 Mbps to 150 Mbps), easing receiver design and improving jitter margin in noisy environments. |
| Low distortion at high frequency | 102 dB SFDR (typ, 1 MHz) and –83 dB THD (5 MHz) support communications and spectral monitoring applications. |
Applications
| High-Speed Imaging | Automated Test Equipment (ATE) |
|---|---|
Use Scenario: Digitizing X-ray detector outputs or time-of-flight LiDAR return pulses with sub-ns timing resolution. IC Role / Device Role / Timing Role: Primary ADC capturing transient analog waveforms at 15 Msps with deterministic latency for trigger synchronization. Use Value: 95.7 dB SNR and 200 MHz input bandwidth preserve signal fidelity across multi-MHz detector bandwidths without aliasing. | Use Scenario: Precision DC parametric testing and AC functional testing of ICs and RF components in production test racks. IC Role / Device Role / Timing Role: High-linearity digitizer for stimulus-response characterization, supporting both static (INL/DNL) and dynamic (SFDR/SNR) test metrics. Use Value: ±3 LSB INL and guaranteed no-missing-codes ensure measurement repeatability across full 18-bit range, reducing calibration overhead. |
| Industrial Control Loops | Communications Signal Monitoring |
Use Scenario: Real-time position/speed feedback in servo drives and motor controllers where loop closure must occur within fixed microsecond windows. IC Role / Device Role / Timing Role: Low-latency ADC feeding FPGA-based PID computation; conversion starts on encoder edge, data ready within 63 ns. Use Value: No pipeline delay allows direct mapping of analog input to control action without added phase lag, improving system stability margins. | Use Scenario: Wideband spectrum analysis in base station monitoring, satellite ground stations, or software-defined radio front ends. IC Role / Device Role / Timing Role: Digitizer for IF or baseband signals up to 7.5 MHz, feeding FFT engines in FPGA or DSP. Use Value: 102 dB SFDR and 95.7 dB SNR enable detection of weak adjacent-channel interferers 100 dB below carriers in dense RF environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8860IRGET | 16-bit, 1 MSPS, SPI interface, 3.3 V supply only; lower power (15 mW), no internal reference. | Lower resolution and speed; suited for portable instrumentation, not high-throughput imaging or ATE. | Select when 16-bit resolution and SPI simplicity outweigh need for 18-bit fidelity and LVDS noise immunity. |
| AD7641ASTZ | 18-bit, 2 MSPS, parallel CMOS interface, 5 V supply; includes internal reference but no LVDS; higher power (45 mW). | Lacks LVDS serialization; requires more PCB routing and suffers greater EMI susceptibility in dense systems. | Select when legacy parallel bus architecture exists and board space permits wider trace routing and additional decoupling. |
Compared with ADS8860IRGET and AD7641ASTZ, the LTC2387IUH-18#PBF uniquely combines 18-bit resolution, 15 Msps speed, LVDS serialization, and integrated reference in a thermally efficient QFN-making it the only option for compact, high-density, high-fidelity acquisition systems demanding deterministic timing.
Availability
LTC2387IUH-18#PBF is available at Aetrix Electronics and suitable for high-speed imaging, automated test equipment, and industrial control loop applications requiring stable component supply across extended temperature ranges.
Supply support for LTC2387IUH-18#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2387IUH-18#PBF belongs to ADI's high-speed precision SAR ADC product line, engineered specifically for applications demanding zero-latency, wide dynamic range, and robust serial interfacing in harsh industrial environments.
FAQ
What is the operating temperature range of the LTC2387IUH-18#PBF?
The LTC2387IUH-18#PBF is rated for operation from –40°C to +85°C, qualifying it for industrial-grade applications including factory automation, outdoor instrumentation, and motor control systems where ambient temperatures exceed commercial limits. This specification is explicitly defined in the Absolute Maximum Ratings table and confirmed across all electrical characteristics with "l" notation indicating full-temperature-range validation.
Does the LTC2387IUH-18#PBF require an external reference?
No, the LTC2387IUH-18#PBF includes a precision internal 2.048 V reference with ±20 ppm/°C maximum temperature coefficient and ±0.25% initial accuracy. The internal reference buffer provides a 4.096 V output on REFBUF pins. An external reference may be applied to REFIN only if higher accuracy or different voltage is needed; otherwise, the internal reference is fully functional and validated across temperature.
How does the LVDS two-lane mode affect timing and layout for the LTC2387IUH-18#PBF?
In two-lane mode (TWOLANES = high), the LTC2387IUH-18#PBF outputs even and odd bits simultaneously on DA+/DA– and DB+/DB–, halving the per-lane data rate from 300 Mbps to 150 Mbps. This relaxes PCB trace length matching and jitter budget requirements. Layout must maintain matched lengths between DA+/DA– and DB+/DB– pairs, and between each pair and DCO+/DCO–, but absolute skew tolerance increases versus one-lane operation.
Can the LTC2387IUH-18#PBF interface directly with a 3.3 V FPGA I/O bank?
No-the LTC2387IUH-18#PBF LVDS outputs (DA+/DA–, DB+/DB–, DCO+/DCO–) are compliant with ANSI TIA/EIA-644-A LVDS standards (differential voltage 247–454 mV, common mode 1.125–1.375 V), not 3.3 V CMOS levels. Direct connection to 3.3 V FPGA banks would violate voltage tolerances. An LVDS-to-CMOS translator or FPGA with native LVDS I/O support is required.
What is the acquisition time (tACQ) specification for the LTC2387IUH-18#PBF at 15 Msps?
At 15 Msps sampling rate, the acquisition time tACQ for the LTC2387IUH-18#PBF is specified as tCYC – 39 ns, where tCYC = 66.6 ns minimum. Thus tACQ ≥ 27.6 ns. This defines the minimum time the analog input must settle before CNV edge to guarantee full 18-bit accuracy; drive circuitry must achieve <0.5 LSB settling within this window.
LTC2387IUH-18#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 18
- Sampling Rate (Per Second):
- 15M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 2.375V ~ 2.625V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-QFN (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2387IUH-18#PBF FAQ
1.How can I place an order for LTC2387IUH-18#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2387IUH-18#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2387IUH-18#PBF reliable?
The price and inventory of LTC2387IUH-18#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2387IUH-18#PBF is usually 5 days.
3.What payment methods are accepted for LTC2387IUH-18#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2387IUH-18#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2387IUH-18#PBF?
LTC2387IUH-18#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2387IUH-18#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2387IUH-18#PBF?
For technical support, including LTC2387IUH-18#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2387IUH-18#PBF requirements.
6.How does Aetrix verify that LTC2387IUH-18#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2387IUH-18#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2387IUH-18#PBF meets industry standards.
7.What is the process for return or replacement of LTC2387IUH-18#PBF?
All LTC2387IUH-18#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2387IUH-18#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2387IUH-18#PBF part is unused and in its original packaging.
Return procedure for LTC2387IUH-18#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2387IUH-18#PBF Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
