My Inquiry
My Account
Analog Devices Inc. LTC2387IUH-18#TRPBF
- Part No.:
- LTC2387IUH-18#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LTC2387IUH-18#TRPBF.pdf
- Description:
- IC ADC 18BIT SAR 32QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,835
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2387IUH-18#TRPBF from Analog Devices (formerly Linear Technology) is an 18-bit, 15 Msps successive approximation register (SAR) analog-to-digital converter with serial LVDS interface, ±4.096 V differential input range, 95.7 dB SNR at 1 MHz, and internal 2.048 V reference. It operates from 5 V and dual 2.5 V supplies and is used in high-speed imaging, instrumentation, and control-loop data acquisition systems.
For engineers reviewing the LTC2387IUH-18#TRPBF datasheet, LTC2387IUH-18#TRPBF pinout, LTC2387IUH-18#TRPBF application, or LTC2387IUH-18#TRPBF equivalent, key selection criteria include guaranteed no missing codes at 18 bits, ±3 LSB INL max over –40°C to +85°C, LVDS one- or two-lane output mode configurability, and 125 mW power dissipation at full throughput.
Technical Context
The LTC2387IUH-18#TRPBF implements a true SAR architecture with no pipeline latency-conversion completes in 63 ns after CNV↑, enabling deterministic timing for closed-loop control. Its fully differential input stage supports Nyquist sampling up to 7.5 MHz with 200 MHz –3 dB input bandwidth and 75 dB CMRR at 1 MHz.
Internal precision circuitry includes a 2.048 V reference with ±20 ppm/°C max drift and a 2× gain reference buffer delivering 4.096 V (±6 mV), both usable with external overdrive. The LVDS interface supports configurable one-lane (18-bit serial) or two-lane (9-bit parallel per lane) output modes, synchronized by DCO echo clock.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 18-bit, guaranteed no missing codes across full temperature range |
| Throughput Rate | 15 Msps maximum, with fixed 66.6 ns minimum cycle time |
| SNR / SINAD | 95.7 dB / 95.7 dB typical at fIN = 1 MHz, defining usable dynamic range |
| INL / DNL | ±3 LSB max INL, ±0.9 LSB max DNL, ensuring monotonicity and linearity-critical measurement fidelity |
| Input Range | ±4.096 V differential (8.192 VP–P), with common-mode range centered at 2.048 V ±0.1 V |
| Power Dissipation | 125 mW at 15 Msps; drops to 10 μW in power-down mode via PD pin |
| Reference | Internal 2.048 V reference (±0.25% initial accuracy), buffered to 4.096 V with ±20 ppm/°C max drift |
Pinout & Package
Package: 32-lead (5 mm × 5 mm) plastic QFN (UH package) with exposed pad (Pin 33) soldered to PCB ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pins 1, 4, 10, 21, 26, 29) | Ground reference | Multiple dedicated ground pins minimize impedance and reduce noise coupling into analog/digital domains |
| IN+, IN– (Pins 2, 3) | Differential analog inputs | Accept ±4.096 V differential signal; require 180° phase alignment and 2.048 V common-mode voltage |
| REFGND (Pins 5, 6) | Reference ground return | Must be shorted together and connected directly to exposed pad and reference bypass capacitors |
| REFBUF (Pins 7, 8) | Buffered reference output | Provides 4.096 V (2× internal reference); bypassed with 10 µF ceramic capacitor to REFGND |
| REFIN (Pin 9) | Internal reference output / external reference input | Outputs 2.048 V; accepts external reference if higher accuracy required; tied to GND to disable internal buffer |
| VDD (Pins 11, 12) | 5 V analog supply | 4.75 V to 5.25 V range; bypassed with 0.1 µF + 10 µF ceramics to GND |
| PD (Pin 13) | Power-down enable | Active-low digital input (OVDD-referenced); reduces total current to 10 µW when asserted |
| CLK+/CLK– (Pins 23, 24) | LVDS clock input | Differential clock input (175–650 mV VID); defines sampling instant and serial data rate |
| DA+/DA–, DB+/DB– (Pins 15–18) | LVDS data outputs | One-lane mode uses DA only; two-lane mode outputs MSB/LSB halves simultaneously on DA/DB |
| DCO+/DCO– (Pins 19, 20) | Data clock output | Echo of CLK; used to latch LVDS data reliably at receiver end |
| CNV+/CNV– (Pins 27, 28) | Conversion start trigger | Differential LVDS input; rising edge initiates sample-and-hold hold phase and conversion |
Key Features
| Feature | Design Value |
|---|---|
| No pipeline latency | Zero-cycle delay enables real-time feedback in servo and control-loop applications |
| Configurable LVDS interface | Selectable one- or two-lane output mode reduces PCB trace count or doubles data rate without changing clock frequency |
| Integrated reference system | On-chip 2.048 V reference + 2× buffer eliminates need for external precision reference in most applications |
| High CMRR & low distortion | 75 dB CMRR at 1 MHz and –101 dB THD at 1 MHz support clean digitization of small signals in noisy environments |
| Robust analog input structure | ESD-protected inputs with 18 pF sampling capacitance and 28 Ω switch resistance enable stable acquisition with low-impedance drive |
Applications
| Medical Ultrasound Imaging | High-Speed ATE Test Systems |
|---|---|
Use Scenario: Digitizing RF echo signals from piezoelectric transducers at multi-MHz rates for beamforming and image reconstruction. IC Role / Device Role / Timing Role: Primary ADC capturing baseband or IF samples with deterministic latency and minimal harmonic distortion. Use Value: 95.7 dB SNR and 102 dB SFDR at 1 MHz preserve weak echo amplitude resolution; no missing codes ensures accurate tissue boundary detection. | Use Scenario: Capturing transient waveforms during functional testing of ASICs, FPGAs, and mixed-signal SoCs at production speed. IC Role / Device Role / Timing Role: High-fidelity waveform capture engine with precise timestamping enabled by CNV-triggered deterministic conversion start. Use Value: 15 Msps throughput and ±3 LSB INL allow pass/fail margin analysis at sub-LSB levels; LVDS interface simplifies high-speed interconnect to test controller. |
| Industrial Closed-Loop Control | Communications Receiver Front-End |
Use Scenario: Sampling current/voltage feedback in motor drives or power converters operating at switching frequencies up to 1 MHz. IC Role / Device Role / Timing Role: Real-time sensor interface with zero-latency conversion for PID loop execution within single PWM cycle. Use Value: No pipeline delay allows control decisions based on latest sample; 125 mW power enables integration into thermally constrained enclosures. | Use Scenario: Digitizing intermediate-frequency (IF) signals in software-defined radio (SDR) receivers requiring wide dynamic range and low spurious content. IC Role / Device Role / Timing Role: High-linearity IF sampling ADC preceding digital downconversion and demodulation. Use Value: 102 dB SFDR at 1 MHz suppresses adjacent-channel interference; 200 MHz input bandwidth supports direct IF sampling up to 7.5 MHz. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8881IDRCT | 18-bit, 10 Msps, SPI interface, external reference required, 3.3 V supply only | Lacks LVDS interface and integrated reference; lower throughput limits control-loop bandwidth | Choose when SPI compatibility, lower power (65 mW), or 3.3 V-only systems outweigh need for LVDS and internal reference |
| AD7641ASTZ | 18-bit, 2 Msps, parallel CMOS interface, ±5 V supplies, no internal reference | Slower throughput and wider supply range suit legacy industrial PLCs but not high-speed imaging | Prefer for cost-sensitive, lower-speed applications where parallel bus simplifies FPGA interfacing and external references are already deployed |
Compared with ADS8881IDRCT and AD7641ASTZ, the LTC2387IUH-18#TRPBF delivers 5× higher throughput than AD7641ASTZ and integrates both reference and LVDS interface-reducing BOM count and layout complexity-while maintaining 18-bit integrity and –40°C to +85°C operation.
Availability
LTC2387IUH-18#TRPBF is available at Aetrix Electronics and suitable for high-speed data acquisition, medical imaging, and industrial control applications requiring stable component supply, extended temperature operation, and long-term obsolescence management.
Supply support for LTC2387IUH-18#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTC2387IUH-18#TRPBF belongs to ADI's high-speed precision SAR ADC product line, designed specifically for applications demanding both wide dynamic range and deterministic low-latency conversion-such as real-time control, ultrasound, and automated test equipment.
FAQ
What is the operating temperature range for the LTC2387IUH-18#TRPBF?
The LTC2387IUH-18#TRPBF is rated for industrial operation from –40°C to +85°C, as indicated by the "I" grade in the part number. This range is validated across all electrical specifications including INL, SNR, and reference stability, making it suitable for deployment in harsh environmental conditions without derating.
Does the LTC2387IUH-18#TRPBF require an external reference?
No-the LTC2387IUH-18#TRPBF includes a factory-trimmed 2.048 V internal reference with ±0.25% initial accuracy and ±20 ppm/°C max drift, plus a 2× gain buffer delivering 4.096 V. An external reference may be applied to REFIN only if higher absolute accuracy or lower drift is required; otherwise, the internal reference is fully functional and production-validated.
How does the LVDS interface of the LTC2387IUH-18#TRPBF support system-level timing integrity?
The LTC2387IUH-18#TRPBF provides a dedicated DCO+ / DCO– echo clock synchronized to the data outputs (DA/DB), eliminating skew-induced setup/hold violations at the receiver. Combined with guaranteed tSKEW (–200 ps to +200 ps), this ensures robust data capture even at 15 Msps without complex PCB length matching-critical for high-reliability test and medical systems.
Can the LTC2387IUH-18#TRPBF operate with a single-ended CNV signal?
Yes-the LTC2387IUH-18#TRPBF supports single-ended CNV operation: tie CNV– to GND and drive CNV+ with a 2.5 V CMOS signal meeting VIH ≥ 1.7 V and VIL ≤ 0.6 V. This simplifies timing generation in systems lacking differential clock resources, while preserving full 15 Msps throughput and specification compliance.
What is the power consumption of the LTC2387IUH-18#TRPBF in active and power-down modes?
In active 15 Msps operation, the LTC2387IUH-18#TRPBF draws 35 mA from VDD (5 V), 31.4 mA from VDDL (2.5 V), and 8.8 mA from OVDD (2.5 V), totaling 125 mW. In power-down mode (PD = low), total current drops to 10 μW-achieved by disabling all analog and digital circuitry including the LVDS drivers-enabling ultra-low-power standby in battery-operated instruments.
LTC2387IUH-18#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 18
- Sampling Rate (Per Second):
- 15M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 2.375V ~ 2.625V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-QFN (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTC2387IUH-18#TRPBF FAQ
1.How can I place an order for LTC2387IUH-18#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2387IUH-18#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2387IUH-18#TRPBF reliable?
The price and inventory of LTC2387IUH-18#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2387IUH-18#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2387IUH-18#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2387IUH-18#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2387IUH-18#TRPBF?
LTC2387IUH-18#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2387IUH-18#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2387IUH-18#TRPBF?
For technical support, including LTC2387IUH-18#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2387IUH-18#TRPBF requirements.
6.How does Aetrix verify that LTC2387IUH-18#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2387IUH-18#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2387IUH-18#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2387IUH-18#TRPBF?
All LTC2387IUH-18#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2387IUH-18#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2387IUH-18#TRPBF part is unused and in its original packaging.
Return procedure for LTC2387IUH-18#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2387IUH-18#TRPBF Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
