My Inquiry
My Account
Analog Devices Inc. LTC2913CMS-2#PBF
- Part No.:
- LTC2913CMS-2#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
LTC2913CMS-2#PBF.pdf
- Description:
- IC SUPERVISOR 2 CHANNEL 10MSOP
- Quantity:
- Payment:
- Shipping:
Inventory:194
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2913CMS-2#PBF from Analog Devices (formerly Linear Technology) is a dual-input, dual-threshold voltage monitor IC designed for simultaneous undervoltage (UV) and overvoltage (OV) supervision of two independent power rails. It features adjustable UV/OV trip points with ±1.5% threshold accuracy, 44 μA quiescent current, open-drain UV/OV outputs, and a dedicated DIS pin to disable both outputs. It is used in desktop/notebook computers and network servers for core/I/O supply monitoring.
For engineers reviewing the LTC2913CMS-2#PBF datasheet, LTC2913CMS-2#PBF pinout, LTC2913CMS-2#PBF application, or LTC2913CMS-2#PBF equivalent, key selection criteria include guaranteed UV/OV assertion down to VCC = 1 V, glitch-filtered comparator inputs, adjustable reset timeout via external capacitor, and explicit output disable functionality - all in a space-constrained 10-lead MSOP package.
Technical Context
The LTC2913CMS-2#PBF implements two independent voltage monitoring channels, each with high-side (VHn) and low-side (VLn) inputs enabling precise UV and OV detection using external resistor dividers. Its internal architecture includes comparator-based sensing with integrated low-pass filtering on each input to reject transients without hysteresis-induced threshold error.
Unlike the LTC2913-1 variant, the -2 version replaces the LATCH pin with a DIS (disable) input that forces both UV and OV outputs into a weakly pulled-high state during normal operation - except under VCC undervoltage lockout (UVLO), where UV asserts low regardless. The TMR pin supports externally programmable timeout periods (6–14 ms typical with 1 nF), and the VCC pin operates as a shunt regulator above 6 V with 6.6 V typical regulation voltage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Operating Range | 2.3 V to 6 V direct supply; >6 V requires series resistor due to internal 6.6 V shunt regulator |
| Threshold Accuracy | ±1.5% over full temperature range - ensures reliable trip point repeatability across 0°C to 70°C (C-grade) |
| Quiescent Current | 44 μA typical - enables micropower system supervision without significant battery drain |
| UV/OV Output Type | Open-drain with weak internal pull-up to VCC - supports wired-OR reset bus and flexible external pull-up selection |
| DIS Input Function | Active-high disable: pulls UV/OV high when asserted, bypassing fault detection except during VCC UVLO |
| Reset Timeout Range | 6–14 ms (typical) set by CTMR capacitor - provides configurable minimum reset pulse width for system settling |
| Input Glitch Rejection | Integrated low-pass filtering per comparator - rejects sub-μs transients without adding hysteresis error |
Pinout & Package
Package: 10-lead MSOP (3mm × 3mm), RoHS-compliant, with exposed pad (optional GND connection). Pin 1 marked with dot; pin numbering follows standard MSOP convention.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VH1 (Pin 1) | Channel 1 High-Side Input | Detects undervoltage when voltage falls below 0.5 V threshold; tied to top of resistor divider for monitored rail |
| VL1 (Pin 2) | Channel 1 Low-Side Input | Detects overvoltage when voltage rises above 0.5 V threshold; tied to bottom of resistor divider |
| VH2 (Pin 3) | Channel 2 High-Side Input | Second UV input - identical function to VH1, enabling dual-rail monitoring |
| VL2 (Pin 4) | Channel 2 Low-Side Input | Second OV input - identical function to VL1 |
| GND (Pin 5) | Ground Reference | Analog and digital ground return; exposed pad may be connected here for thermal performance |
| OV (Pin 6) | Overvoltage Output | Open-drain logic output asserted low during OV condition; weakly pulled high when inactive or disabled |
| UV (Pin 7) | Undervoltage Output | Open-drain logic output asserted low during UV condition; remains active during VCC UVLO even if DIS is high |
| DIS (Pin 8) | Output Disable Control | Active-high input: disables UV/OV assertion except during VCC UVLO; internal 2 μA pull-down ensures safe default state |
| TMR (Pin 9) | Timeout Timer Input | Connects to external capacitor (≥10 pF) to set reset pulse duration; tie to VCC to bypass timeout |
| VCC (Pin 10) | Supply Voltage Input | Power input with internal shunt regulator; bypass with ≥0.1 μF capacitor; functional down to 1 V |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent UV/OV monitoring | Supervises two separate power rails simultaneously using four analog inputs (VH1/VL1, VH2/VL2) |
| Adjustable trip thresholds | Set via external resistor dividers - supports custom UV/OV points for any nominal rail (e.g., 5 V, 3.3 V, 12 V) |
| Guaranteed operation at low VCC | UV/OV outputs fully functional down to VCC = 1 V - critical for brown-out detection in battery-backed systems |
| Glitch-immune comparator inputs | Internal RC filtering rejects fast transients without hysteresis, preserving ±1.5% threshold accuracy |
| Configurable reset timeout | External capacitor on TMR pin sets delay (e.g., 200 ms with 22 nF) - ensures sufficient system settling after fault clearance |
Applications
| Desktop Computer Power Sequencing | Notebook Computer Battery Management |
|---|---|
Use Scenario: Monitoring +12 V, +5 V, and +3.3 V rails during cold boot and dynamic load changes. IC Role / Device Role / Timing Role: LTC2913CMS-2#PBF acts as dual-rail supervisor, asserting coordinated UV/OV signals to motherboard CPLD for controlled power sequencing and fault shutdown. Use Value: Prevents CPU/GPU instability by enforcing strict voltage validity windows before release of processor reset, leveraging ±1.5% threshold accuracy and glitch immunity. | Use Scenario: Supervising main system rail (5 V) and USB-C PD interface rail (3.3 V) in portable designs with tight power budgets. IC Role / Device Role / Timing Role: LTC2913CMS-2#PBF provides low-quiescent-current (44 μA) dual-rail monitoring, with DIS pin used to gate reset signals during sleep mode transitions. Use Value: Enables zero-power reset hold during suspend states while maintaining fast wake-up response - DIS pin disables outputs without disabling internal comparators. |
| Network Server Core Voltage Monitoring | Industrial Embedded Controller I/O Supply Supervision |
Use Scenario: Continuous monitoring of FPGA core (1.2 V) and I/O bank (2.5 V) supplies in 24/7 data center equipment. IC Role / Device Role / Timing Role: LTC2913CMS-2#PBF serves as fail-safe voltage guardian, triggering system watchdog reset via UV/OV outputs upon sustained rail deviation beyond ±10%. Use Value: Ensures deterministic recovery from voltage sags caused by sudden load transients - achieved via adjustable TMR timeout and accurate 0.5 V internal reference. | Use Scenario: Supervising isolated 5 V and 24 V I/O power domains in PLC backplanes subject to EMI and load switching noise. IC Role / Device Role / Timing Role: LTC2913CMS-2#PBF functions as noise-hardened dual-supply monitor, using built-in input filtering to reject conducted EMI without external RC networks. Use Value: Eliminates spurious resets in electrically noisy environments - validated by transient duration vs. overdrive curves showing immunity to <1 μs glitches. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UV/OV monitoring applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC2913CDD-2#PBF | Same electrical specs and DIS functionality; differs only in 3mm × 3mm DFN package with exposed thermal pad | Preferred for thermally constrained layouts or higher power dissipation scenarios requiring enhanced thermal performance | Select when PCB layout allows DFN footprint and thermal management benefits outweigh MSOP rework familiarity |
| LTC2904CMS8#PBF | 3-state programmable dual supply monitor; no DIS pin; fixed 1.25 V reference; ±0.75% threshold accuracy; 8-lead SOT-23 | Offers tighter threshold tolerance but lacks output disable and adjustable timeout; limited to lower-voltage rails (≤6 V) | Choose when highest accuracy is required for single-rail monitoring and board space is extremely limited |
Compared with LTC2913CDD-2#PBF, the LTC2913CMS-2#PBF offers identical supervision logic in a more familiar MSOP package with established reflow profiles; versus LTC2904CMS8#PBF, it trades absolute accuracy for robust disable control, wider VCC range, and field-configurable timeout - making it superior for multi-rail industrial and computing systems requiring fault-gating flexibility.
Availability
LTC2913CMS-2#PBF is available at Aetrix Electronics and suitable for desktop computers, notebook computers, and network servers requiring stable component supply with guaranteed long-term manufacturability and consistent parametric performance.
Supply support for LTC2913CMS-2#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its precision analog portfolio, including high-reliability supervisory ICs engineered for mission-critical power integrity.
The LTC2913 product line was designed specifically for space-constrained, low-power dual-rail voltage monitoring in computing and communications infrastructure - emphasizing micropower operation, glitch immunity, and flexible output control.
FAQ
What is the function of the DIS pin on the LTC2913CMS-2#PBF?
The DIS (disable) pin on the LTC2913CMS-2#PBF is an active-high control input that forces both UV and OV outputs into a weakly pulled-high state, effectively disabling fault reporting. When DIS is high, UV and OV remain deasserted regardless of input conditions - except during VCC undervoltage lockout (UVLO), where UV asserts low to signal supply failure. The pin has a 2 μA internal pull-down, allowing safe operation with an unconnected pin. This behavior distinguishes the LTC2913CMS-2#PBF from the -1 variant, which uses LATCH instead.
Can the LTC2913CMS-2#PBF monitor negative voltages?
No, the LTC2913CMS-2#PBF is designed exclusively for positive voltage monitoring. Its VHn and VLn inputs operate with respect to GND and require input voltages between –0.3 V and 7.5 V. For negative rail supervision, Analog Devices offers the LTC2909 or LTC2914, which support dedicated negative voltage inputs and separate VCC biasing. The LTC2913CMS-2#PBF's internal 0.5 V threshold reference is fixed and referenced to GND, making it unsuitable for direct negative rail detection without external level-shifting circuitry - which is not supported by its architecture or Absolute Maximum Ratings.
What is the minimum VCC voltage required for valid UV/OV output assertion in the LTC2913CMS-2#PBF?
The LTC2913CMS-2#PBF guarantees valid UV and OV output assertion down to VCC = 1 V. Below this, functionality is not specified. At VCC ≥ 1 V, the device asserts UV low and OV weakly pulls high during power-up, and maintains correct comparator operation and output drive strength. The datasheet specifies VOL ≤ 0.15 V at UV with VCC = 1 V and IUV = 100 μA, confirming functional low-state drive capability even at minimum supply. This ultra-low VCC operation enables brown-out detection in battery-powered or energy-harvesting systems where supply collapse must be captured early.
How does the TMR pin affect reset timing in the LTC2913CMS-2#PBF?
The TMR pin on the LTC2913CMS-2#PBF sets the reset timeout period (tUOTO) via an external capacitor to GND. The relationship is approximately tUOTO ≈ 9 ms/nF, so a 1 nF capacitor yields ~8.5 ms timeout. This timeout holds UV/OV asserted after all faults clear, ensuring a minimum reset pulse width for system stabilization. If TMR is tied to VCC, the timeout is bypassed and outputs respond immediately to input recovery. Capacitor leakage must stay below 1.3 μA to avoid timing drift. The LTC2913CMS-2#PBF's TMR circuit is identical to that of the -1 variant - only the DIS/LATCH pin function differs between versions.
Is the LTC2913CMS-2#PBF pin-compatible with other LTC2913 variants?
Yes, the LTC2913CMS-2#PBF is pin-compatible with all other MSOP-packaged LTC2913 variants (e.g., LTC2913CMS-1#PBF, LTC2913IMS-2#PBF), sharing identical 10-pin MSOP footprints and pin assignments. The only functional difference lies in Pin 8: LTC2913CMS-2#PBF uses DIS (disable), while LTC2913CMS-1#PBF uses LATCH (OV latch clear). Swapping them without updating firmware or external logic may cause unintended behavior - e.g., tying LATCH high on a -1 part mimics DIS functionality, but pulling DIS low on a -2 part has no effect. Electrical compatibility is maintained; mechanical fit is identical.
LTC2913CMS-2#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 2
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-MSOP
LTC2913CMS-2#PBF FAQ
1.How can I place an order for LTC2913CMS-2#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2913CMS-2#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2913CMS-2#PBF reliable?
The price and inventory of LTC2913CMS-2#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2913CMS-2#PBF is usually 5 days.
3.What payment methods are accepted for LTC2913CMS-2#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2913CMS-2#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2913CMS-2#PBF?
LTC2913CMS-2#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2913CMS-2#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2913CMS-2#PBF?
For technical support, including LTC2913CMS-2#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2913CMS-2#PBF requirements.
6.How does Aetrix verify that LTC2913CMS-2#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2913CMS-2#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2913CMS-2#PBF meets industry standards.
7.What is the process for return or replacement of LTC2913CMS-2#PBF?
All LTC2913CMS-2#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2913CMS-2#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2913CMS-2#PBF part is unused and in its original packaging.
Return procedure for LTC2913CMS-2#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2913CMS-2#PBF Tags
-
MIC826SYMT-TR
Microchip Technology
-
APX803S-31SA-7
Diodes Incorporated
-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments
-
V6340RSP3B+
EM Microelectronic
-
EM6325CXSP5B-2.9+
EM Microelectronic
-
MCP120T-300I/TT
Microchip Technology
-
MCP130T-315I/TT
Microchip Technology
-
MCP120T-475I/TT
Microchip Technology
-
MCP111T-300E/TT
Microchip Technology
-
MCP120T-315I/TT
Microchip Technology
-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
